Files
bare_metal
bit_field
bl602_hal
bl602_pac
aon
cci
cks
dma
ef_ctrl
ef_data_0
ef_data_1
glb
gpip
hbn
i2c
ir
l1c
pds
pwm
rf
adda1.rsadda2.rsadda_reg_ctrl_hw.rscip.rsdfe_ctrl_0.rsdfe_ctrl_1.rsdfe_ctrl_10.rsdfe_ctrl_11.rsdfe_ctrl_12.rsdfe_ctrl_13.rsdfe_ctrl_14.rsdfe_ctrl_15.rsdfe_ctrl_16.rsdfe_ctrl_17.rsdfe_ctrl_18.rsdfe_ctrl_2.rsdfe_ctrl_3.rsdfe_ctrl_4.rsdfe_ctrl_5.rsdfe_ctrl_6.rsdfe_ctrl_7.rsdfe_ctrl_8.rsdfe_ctrl_9.rsfbdv.rslna.rslna_ctrl_hw_mux.rslo.rslo_cal_ctrl_hw1.rslo_cal_ctrl_hw10.rslo_cal_ctrl_hw11.rslo_cal_ctrl_hw2.rslo_cal_ctrl_hw3.rslo_cal_ctrl_hw4.rslo_cal_ctrl_hw5.rslo_cal_ctrl_hw6.rslo_cal_ctrl_hw7.rslo_cal_ctrl_hw8.rslo_cal_ctrl_hw9.rslo_reg_ctrl_hw1.rslo_sdm_ctrl_hw1.rslo_sdm_ctrl_hw2.rslo_sdm_ctrl_hw3.rslo_sdm_ctrl_hw4.rslo_sdm_ctrl_hw5.rslo_sdm_ctrl_hw6.rslo_sdm_ctrl_hw7.rslo_sdm_ctrl_hw8.rslodist.rspa1.rspa2.rspa_reg_ctrl_hw1.rspa_reg_ctrl_hw2.rspa_reg_wifi_ctrl_hw.rspfdcp.rspmip_mv2aon.rsppu_ctrl_hw.rspucr1.rspucr1_hw.rspucr2.rspucr2_hw.rspud_ctrl_hw.rsrbb1.rsrbb2.rsrbb3.rsrbb4.rsrbb_bw_ctrl_hw.rsrbb_gain_index1.rsrbb_gain_index2.rsrbb_gain_index3.rsrbb_gain_index4.rsrbb_gain_index5.rsrf_base_ctrl1.rsrf_base_ctrl2.rsrf_data_temp_0.rsrf_data_temp_1.rsrf_data_temp_2.rsrf_data_temp_3.rsrf_fsm_ctrl0.rsrf_fsm_ctrl1.rsrf_fsm_ctrl2.rsrf_fsm_ctrl_hw.rsrf_fsm_ctrl_sw.rsrf_ical_ctrl0.rsrf_ical_ctrl1.rsrf_ical_ctrl2.rsrf_pkdet_ctrl0.rsrf_resv_reg_0.rsrf_resv_reg_1.rsrf_resv_reg_2.rsrf_rev.rsrf_sram_ctrl0.rsrf_sram_ctrl1.rsrf_sram_ctrl2.rsrf_sram_ctrl3.rsrf_sram_ctrl4.rsrf_sram_ctrl5.rsrf_sram_ctrl6.rsrfcal_ctrlen.rsrfcal_stateen.rsrfcal_status.rsrfcal_status2.rsrfctrl_hw_en.rsrfif_dfe_ctrl0.rsrfif_dig_ctrl.rsrfif_test_read.rsrmxgm.rsrosdac_ctrl_hw1.rsrosdac_ctrl_hw2.rsrrf_gain_index1.rsrrf_gain_index2.rsrxiq_ctrl_hw1.rsrxiq_ctrl_hw2.rsrxiq_ctrl_hw3.rsrxiq_ctrl_hw4.rssaradc_resv.rssdm1.rssdm2.rssdm3.rssingen_ctrl0.rssingen_ctrl1.rssingen_ctrl2.rssingen_ctrl3.rssingen_ctrl4.rstbb.rstbb_gain_index1.rstbb_gain_index2.rstbb_gain_index3.rstbb_gain_index4.rstemp_comp.rsten_ac.rsten_dc.rsten_dig.rstmx.rstosdac_ctrl_hw1.rstosdac_ctrl_hw2.rstosdac_ctrl_hw3.rstosdac_ctrl_hw4.rstrx_gain1.rstrx_gain_hw.rstx_iq_gain_hw0.rstx_iq_gain_hw1.rstx_iq_gain_hw2.rstx_iq_gain_hw3.rstx_iq_gain_hw4.rstx_iq_gain_hw5.rstx_iq_gain_hw6.rstx_iq_gain_hw7.rsvco1.rsvco2.rsvco3.rsvco4.rs
sec_dbg
sec_eng
se_aes_0_ctrl.rsse_aes_0_ctrl_prot.rsse_aes_0_endian.rsse_aes_0_iv_0.rsse_aes_0_iv_1.rsse_aes_0_iv_2.rsse_aes_0_iv_3.rsse_aes_0_key_0.rsse_aes_0_key_1.rsse_aes_0_key_2.rsse_aes_0_key_3.rsse_aes_0_key_4.rsse_aes_0_key_5.rsse_aes_0_key_6.rsse_aes_0_key_7.rsse_aes_0_key_sel_0.rsse_aes_0_key_sel_1.rsse_aes_0_link.rsse_aes_0_mda.rsse_aes_0_msa.rsse_aes_0_sboot.rsse_aes_0_status.rsse_cdet_0_ctrl_0.rsse_cdet_0_ctrl_1.rsse_cdet_0_ctrl_prot.rsse_ctrl_prot_rd.rsse_ctrl_reserved_0.rsse_ctrl_reserved_1.rsse_ctrl_reserved_2.rsse_gmac_0_ctrl_0.rsse_gmac_0_ctrl_prot.rsse_gmac_0_lca.rsse_gmac_0_status.rsse_pka_0_ctrl_0.rsse_pka_0_ctrl_1.rsse_pka_0_ctrl_prot.rsse_pka_0_rw.rsse_pka_0_rw_burst.rsse_pka_0_seed.rsse_sha_0_ctrl.rsse_sha_0_ctrl_prot.rsse_sha_0_endian.rsse_sha_0_hash_h_0.rsse_sha_0_hash_h_1.rsse_sha_0_hash_h_2.rsse_sha_0_hash_h_3.rsse_sha_0_hash_h_4.rsse_sha_0_hash_h_5.rsse_sha_0_hash_h_6.rsse_sha_0_hash_h_7.rsse_sha_0_hash_l_0.rsse_sha_0_hash_l_1.rsse_sha_0_hash_l_2.rsse_sha_0_hash_l_3.rsse_sha_0_hash_l_4.rsse_sha_0_hash_l_5.rsse_sha_0_hash_l_6.rsse_sha_0_hash_l_7.rsse_sha_0_link.rsse_sha_0_msa.rsse_sha_0_status.rsse_trng_0_ctrl_0.rsse_trng_0_ctrl_1.rsse_trng_0_ctrl_2.rsse_trng_0_ctrl_3.rsse_trng_0_ctrl_prot.rsse_trng_0_dout_0.rsse_trng_0_dout_1.rsse_trng_0_dout_2.rsse_trng_0_dout_3.rsse_trng_0_dout_4.rsse_trng_0_dout_5.rsse_trng_0_dout_6.rsse_trng_0_dout_7.rsse_trng_0_status.rsse_trng_0_test.rsse_trng_0_test_out_0.rsse_trng_0_test_out_1.rsse_trng_0_test_out_2.rsse_trng_0_test_out_3.rs
sf_ctrl
spi
timer
tzc_nsec
tzc_sec
uart
bl602_rust_guide
embedded_hal
embedded_time
nb
num
num_complex
num_integer
num_iter
num_rational
num_traits
panic_halt
r0
riscv
riscv_rt
vcell
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27
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29
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macro_rules! reg {
    (
        $addr:expr, $csr:ident, $readf:ident, $writef:ident
    ) => {
        /// Machine performance-monitoring event selector
        pub mod $csr {
            read_csr_as_usize!($addr, $readf);
            write_csr_as_usize!($addr, $writef);
        }
    };
}

reg!(0x323, mhpmevent3, __read_mhpmevent3, __write_mhpmevent3);
reg!(0x324, mhpmevent4, __read_mhpmevent4, __write_mhpmevent4);
reg!(0x325, mhpmevent5, __read_mhpmevent5, __write_mhpmevent5);
reg!(0x326, mhpmevent6, __read_mhpmevent6, __write_mhpmevent6);
reg!(0x327, mhpmevent7, __read_mhpmevent7, __write_mhpmevent7);
reg!(0x328, mhpmevent8, __read_mhpmevent8, __write_mhpmevent8);
reg!(0x329, mhpmevent9, __read_mhpmevent9, __write_mhpmevent9);
reg!(0x32A, mhpmevent10, __read_mhpmevent10, __write_mhpmevent10);
reg!(0x32B, mhpmevent11, __read_mhpmevent11, __write_mhpmevent11);
reg!(0x32C, mhpmevent12, __read_mhpmevent12, __write_mhpmevent12);
reg!(0x32D, mhpmevent13, __read_mhpmevent13, __write_mhpmevent13);
reg!(0x32E, mhpmevent14, __read_mhpmevent14, __write_mhpmevent14);
reg!(0x32F, mhpmevent15, __read_mhpmevent15, __write_mhpmevent15);
reg!(0x330, mhpmevent16, __read_mhpmevent16, __write_mhpmevent16);
reg!(0x331, mhpmevent17, __read_mhpmevent17, __write_mhpmevent17);
reg!(0x332, mhpmevent18, __read_mhpmevent18, __write_mhpmevent18);
reg!(0x333, mhpmevent19, __read_mhpmevent19, __write_mhpmevent19);
reg!(0x334, mhpmevent20, __read_mhpmevent20, __write_mhpmevent20);
reg!(0x335, mhpmevent21, __read_mhpmevent21, __write_mhpmevent21);
reg!(0x336, mhpmevent22, __read_mhpmevent22, __write_mhpmevent22);
reg!(0x337, mhpmevent23, __read_mhpmevent23, __write_mhpmevent23);
reg!(0x338, mhpmevent24, __read_mhpmevent24, __write_mhpmevent24);
reg!(0x339, mhpmevent25, __read_mhpmevent25, __write_mhpmevent25);
reg!(0x33A, mhpmevent26, __read_mhpmevent26, __write_mhpmevent26);
reg!(0x33B, mhpmevent27, __read_mhpmevent27, __write_mhpmevent27);
reg!(0x33C, mhpmevent28, __read_mhpmevent28, __write_mhpmevent28);
reg!(0x33D, mhpmevent29, __read_mhpmevent29, __write_mhpmevent29);
reg!(0x33E, mhpmevent30, __read_mhpmevent30, __write_mhpmevent30);
reg!(0x33F, mhpmevent31, __read_mhpmevent31, __write_mhpmevent31);