mideleg.rs.html -- source

Files

bare_metal

bit_field

bl602_hal

clock.rs gpio.rs lib.rs serial.rs

bl602_pac

aon

cci

cci_addr.rs cci_cfg.rs cci_ctl.rs cci_rdata.rs cci_wdata.rs

cks

cks_config.rs cks_out.rs data_in.rs

dma

ef_ctrl

ef_crc_ctrl_0.rs ef_crc_ctrl_1.rs ef_crc_ctrl_2.rs ef_crc_ctrl_3.rs ef_crc_ctrl_4.rs ef_crc_ctrl_5.rs ef_if_0_manual.rs ef_if_0_status.rs ef_if_ana_trim_0.rs ef_if_cfg_0.rs ef_if_ctrl_0.rs ef_if_cyc_0.rs ef_if_cyc_1.rs ef_if_sw_usage_0.rs ef_reserved.rs ef_sw_cfg_0.rs

ef_data_0

ef_data_1

glb

bmx_cfg1.rs bmx_cfg2.rs bmx_dbg_out.rs bmx_err_addr.rs cgen_cfg0.rs cgen_cfg1.rs cgen_cfg2.rs cgen_cfg3.rs clk_cfg0.rs clk_cfg1.rs clk_cfg2.rs clk_cfg3.rs cpu_clk_cfg.rs dbg_sel_hh.rs dbg_sel_hl.rs dbg_sel_lh.rs dbg_sel_ll.rs debug.rs dig32k_wakeup_ctrl.rs glb_parm.rs gpadc_32m_src_ctrl.rs gpdac_actrl.rs gpdac_bctrl.rs gpdac_ctrl.rs gpdac_data.rs gpio_cfgctl0.rs gpio_cfgctl1.rs gpio_cfgctl10.rs gpio_cfgctl11.rs gpio_cfgctl12.rs gpio_cfgctl13.rs gpio_cfgctl14.rs gpio_cfgctl2.rs gpio_cfgctl3.rs gpio_cfgctl30.rs gpio_cfgctl31.rs gpio_cfgctl32.rs gpio_cfgctl33.rs gpio_cfgctl34.rs gpio_cfgctl35.rs gpio_cfgctl4.rs gpio_cfgctl5.rs gpio_cfgctl6.rs gpio_cfgctl7.rs gpio_cfgctl8.rs gpio_cfgctl9.rs gpio_int_clr1.rs gpio_int_mask1.rs gpio_int_mode_set1.rs gpio_int_mode_set2.rs gpio_int_mode_set3.rs gpio_int_stat1.rs led_driver.rs mbist_ctl.rs mbist_stat.rs rsv0.rs rsv1.rs rsv2.rs rsv3.rs seam_misc.rs sram_parm.rs sram_ret.rs sram_slp.rs swrst_cfg0.rs swrst_cfg1.rs swrst_cfg2.rs swrst_cfg3.rs tzc_glb_ctrl_0.rs tzc_glb_ctrl_1.rs tzc_glb_ctrl_2.rs tzc_glb_ctrl_3.rs uart_sig_sel_0.rs wifi_bt_coex_ctrl.rs

gpip

gpadc_config.rs gpadc_dma_rdata.rs gpdac_config.rs gpdac_dma_config.rs gpdac_dma_wdata.rs gpdac_tx_fifo_status.rs

hbn

i2c

i2c_bus_busy.rs i2c_config.rs i2c_fifo_config_0.rs i2c_fifo_config_1.rs i2c_fifo_rdata.rs i2c_fifo_wdata.rs i2c_int_sts.rs i2c_prd_data.rs i2c_prd_start.rs i2c_prd_stop.rs i2c_sub_addr.rs

ir

l1c

cpu_clk_gate.rs hit_cnt_lsb.rs hit_cnt_msb.rs irom1_misr_dataout_0.rs irom1_misr_dataout_1.rs l1c_bmx_err_addr.rs l1c_bmx_err_addr_en.rs l1c_config.rs l1c_range.rs miss_cnt.rs

pds

clkpll_cp.rs clkpll_fbdv.rs clkpll_output_en.rs clkpll_rz.rs clkpll_sdm.rs clkpll_top_ctrl.rs clkpll_vco.rs pds_ctl.rs pds_ctl2.rs pds_ctl3.rs pds_ctl4.rs pds_int.rs pds_ram1.rs pds_stat.rs pds_time1.rs pu_rst_clkpll.rs rc32m_ctrl0.rs rc32m_ctrl1.rs

pwm

rf

adda1.rs adda2.rs adda_reg_ctrl_hw.rs cip.rs dfe_ctrl_0.rs dfe_ctrl_1.rs dfe_ctrl_10.rs dfe_ctrl_11.rs dfe_ctrl_12.rs dfe_ctrl_13.rs dfe_ctrl_14.rs dfe_ctrl_15.rs dfe_ctrl_16.rs dfe_ctrl_17.rs dfe_ctrl_18.rs dfe_ctrl_2.rs dfe_ctrl_3.rs dfe_ctrl_4.rs dfe_ctrl_5.rs dfe_ctrl_6.rs dfe_ctrl_7.rs dfe_ctrl_8.rs dfe_ctrl_9.rs fbdv.rs lna.rs lna_ctrl_hw_mux.rs lo.rs lo_cal_ctrl_hw1.rs lo_cal_ctrl_hw10.rs lo_cal_ctrl_hw11.rs lo_cal_ctrl_hw2.rs lo_cal_ctrl_hw3.rs lo_cal_ctrl_hw4.rs lo_cal_ctrl_hw5.rs lo_cal_ctrl_hw6.rs lo_cal_ctrl_hw7.rs lo_cal_ctrl_hw8.rs lo_cal_ctrl_hw9.rs lo_reg_ctrl_hw1.rs lo_sdm_ctrl_hw1.rs lo_sdm_ctrl_hw2.rs lo_sdm_ctrl_hw3.rs lo_sdm_ctrl_hw4.rs lo_sdm_ctrl_hw5.rs lo_sdm_ctrl_hw6.rs lo_sdm_ctrl_hw7.rs lo_sdm_ctrl_hw8.rs lodist.rs pa1.rs pa2.rs pa_reg_ctrl_hw1.rs pa_reg_ctrl_hw2.rs pa_reg_wifi_ctrl_hw.rs pfdcp.rs pmip_mv2aon.rs ppu_ctrl_hw.rs pucr1.rs pucr1_hw.rs pucr2.rs pucr2_hw.rs pud_ctrl_hw.rs rbb1.rs rbb2.rs rbb3.rs rbb4.rs rbb_bw_ctrl_hw.rs rbb_gain_index1.rs rbb_gain_index2.rs rbb_gain_index3.rs rbb_gain_index4.rs rbb_gain_index5.rs rf_base_ctrl1.rs rf_base_ctrl2.rs rf_data_temp_0.rs rf_data_temp_1.rs rf_data_temp_2.rs rf_data_temp_3.rs rf_fsm_ctrl0.rs rf_fsm_ctrl1.rs rf_fsm_ctrl2.rs rf_fsm_ctrl_hw.rs rf_fsm_ctrl_sw.rs rf_ical_ctrl0.rs rf_ical_ctrl1.rs rf_ical_ctrl2.rs rf_pkdet_ctrl0.rs rf_resv_reg_0.rs rf_resv_reg_1.rs rf_resv_reg_2.rs rf_rev.rs rf_sram_ctrl0.rs rf_sram_ctrl1.rs rf_sram_ctrl2.rs rf_sram_ctrl3.rs rf_sram_ctrl4.rs rf_sram_ctrl5.rs rf_sram_ctrl6.rs rfcal_ctrlen.rs rfcal_stateen.rs rfcal_status.rs rfcal_status2.rs rfctrl_hw_en.rs rfif_dfe_ctrl0.rs rfif_dig_ctrl.rs rfif_test_read.rs rmxgm.rs rosdac_ctrl_hw1.rs rosdac_ctrl_hw2.rs rrf_gain_index1.rs rrf_gain_index2.rs rxiq_ctrl_hw1.rs rxiq_ctrl_hw2.rs rxiq_ctrl_hw3.rs rxiq_ctrl_hw4.rs saradc_resv.rs sdm1.rs sdm2.rs sdm3.rs singen_ctrl0.rs singen_ctrl1.rs singen_ctrl2.rs singen_ctrl3.rs singen_ctrl4.rs tbb.rs tbb_gain_index1.rs tbb_gain_index2.rs tbb_gain_index3.rs tbb_gain_index4.rs temp_comp.rs ten_ac.rs ten_dc.rs ten_dig.rs tmx.rs tosdac_ctrl_hw1.rs tosdac_ctrl_hw2.rs tosdac_ctrl_hw3.rs tosdac_ctrl_hw4.rs trx_gain1.rs trx_gain_hw.rs tx_iq_gain_hw0.rs tx_iq_gain_hw1.rs tx_iq_gain_hw2.rs tx_iq_gain_hw3.rs tx_iq_gain_hw4.rs tx_iq_gain_hw5.rs tx_iq_gain_hw6.rs tx_iq_gain_hw7.rs vco1.rs vco2.rs vco3.rs vco4.rs

sec_dbg

sd_chip_id_high.rs sd_chip_id_low.rs sd_dbg_pwd_high.rs sd_dbg_pwd_low.rs sd_dbg_reserved.rs sd_status.rs sd_wifi_mac_high.rs sd_wifi_mac_low.rs

sec_eng

se_aes_0_ctrl.rs se_aes_0_ctrl_prot.rs se_aes_0_endian.rs se_aes_0_iv_0.rs se_aes_0_iv_1.rs se_aes_0_iv_2.rs se_aes_0_iv_3.rs se_aes_0_key_0.rs se_aes_0_key_1.rs se_aes_0_key_2.rs se_aes_0_key_3.rs se_aes_0_key_4.rs se_aes_0_key_5.rs se_aes_0_key_6.rs se_aes_0_key_7.rs se_aes_0_key_sel_0.rs se_aes_0_key_sel_1.rs se_aes_0_link.rs se_aes_0_mda.rs se_aes_0_msa.rs se_aes_0_sboot.rs se_aes_0_status.rs se_cdet_0_ctrl_0.rs se_cdet_0_ctrl_1.rs se_cdet_0_ctrl_prot.rs se_ctrl_prot_rd.rs se_ctrl_reserved_0.rs se_ctrl_reserved_1.rs se_ctrl_reserved_2.rs se_gmac_0_ctrl_0.rs se_gmac_0_ctrl_prot.rs se_gmac_0_lca.rs se_gmac_0_status.rs se_pka_0_ctrl_0.rs se_pka_0_ctrl_1.rs se_pka_0_ctrl_prot.rs se_pka_0_rw.rs se_pka_0_rw_burst.rs se_pka_0_seed.rs se_sha_0_ctrl.rs se_sha_0_ctrl_prot.rs se_sha_0_endian.rs se_sha_0_hash_h_0.rs se_sha_0_hash_h_1.rs se_sha_0_hash_h_2.rs se_sha_0_hash_h_3.rs se_sha_0_hash_h_4.rs se_sha_0_hash_h_5.rs se_sha_0_hash_h_6.rs se_sha_0_hash_h_7.rs se_sha_0_hash_l_0.rs se_sha_0_hash_l_1.rs se_sha_0_hash_l_2.rs se_sha_0_hash_l_3.rs se_sha_0_hash_l_4.rs se_sha_0_hash_l_5.rs se_sha_0_hash_l_6.rs se_sha_0_hash_l_7.rs se_sha_0_link.rs se_sha_0_msa.rs se_sha_0_status.rs se_trng_0_ctrl_0.rs se_trng_0_ctrl_1.rs se_trng_0_ctrl_2.rs se_trng_0_ctrl_3.rs se_trng_0_ctrl_prot.rs se_trng_0_dout_0.rs se_trng_0_dout_1.rs se_trng_0_dout_2.rs se_trng_0_dout_3.rs se_trng_0_dout_4.rs se_trng_0_dout_5.rs se_trng_0_dout_6.rs se_trng_0_dout_7.rs se_trng_0_status.rs se_trng_0_test.rs se_trng_0_test_out_0.rs se_trng_0_test_out_1.rs se_trng_0_test_out_2.rs se_trng_0_test_out_3.rs

sf_ctrl

sf2_if_io_dly_0.rs sf2_if_io_dly_1.rs sf2_if_io_dly_2.rs sf2_if_io_dly_3.rs sf2_if_io_dly_4.rs sf3_if_io_dly_0.rs sf3_if_io_dly_1.rs sf3_if_io_dly_2.rs sf3_if_io_dly_3.rs sf3_if_io_dly_4.rs sf_aes.rs sf_aes_cfg_r0.rs sf_aes_iv_r0_w0.rs sf_aes_iv_r0_w1.rs sf_aes_iv_r0_w2.rs sf_aes_iv_r0_w3.rs sf_aes_iv_r1_w0.rs sf_aes_iv_r1_w1.rs sf_aes_iv_r1_w2.rs sf_aes_iv_r1_w3.rs sf_aes_iv_r2_w0.rs sf_aes_iv_r2_w1.rs sf_aes_iv_r2_w2.rs sf_aes_iv_r2_w3.rs sf_aes_key_r0_0.rs sf_aes_key_r0_1.rs sf_aes_key_r0_2.rs sf_aes_key_r0_3.rs sf_aes_key_r0_4.rs sf_aes_key_r0_5.rs sf_aes_key_r0_6.rs sf_aes_key_r0_7.rs sf_aes_key_r1_0.rs sf_aes_key_r1_1.rs sf_aes_key_r1_2.rs sf_aes_key_r1_3.rs sf_aes_key_r1_4.rs sf_aes_key_r1_5.rs sf_aes_key_r1_6.rs sf_aes_key_r1_7.rs sf_aes_key_r2_0.rs sf_aes_key_r2_1.rs sf_aes_key_r2_2.rs sf_aes_key_r2_3.rs sf_aes_key_r2_4.rs sf_aes_key_r2_5.rs sf_aes_key_r2_6.rs sf_aes_key_r2_7.rs sf_aes_r1.rs sf_aes_r2.rs sf_ahb2sif_status.rs sf_ctrl_0.rs sf_ctrl_1.rs sf_ctrl_2.rs sf_ctrl_3.rs sf_ctrl_prot_en.rs sf_ctrl_prot_en_rd.rs sf_id0_offset.rs sf_id1_offset.rs sf_if_iahb_0.rs sf_if_iahb_1.rs sf_if_iahb_2.rs sf_if_iahb_3.rs sf_if_iahb_4.rs sf_if_iahb_5.rs sf_if_iahb_6.rs sf_if_iahb_7.rs sf_if_io_dly_0.rs sf_if_io_dly_1.rs sf_if_io_dly_2.rs sf_if_io_dly_3.rs sf_if_io_dly_4.rs sf_if_sahb_0.rs sf_if_sahb_1.rs sf_if_sahb_2.rs sf_if_status_0.rs sf_if_status_1.rs sf_reserved.rs

spi

spi_bus_busy.rs spi_config.rs spi_fifo_config_0.rs spi_fifo_config_1.rs spi_fifo_rdata.rs spi_fifo_wdata.rs spi_int_sts.rs spi_prd_0.rs spi_prd_1.rs spi_rxd_ignr.rs spi_sto_value.rs

timer

tzc_nsec

tzc_rom0_r0.rs tzc_rom0_r1.rs tzc_rom1_r0.rs tzc_rom1_r1.rs tzc_rom_ctrl.rs

tzc_sec

tzc_rom0_r0.rs tzc_rom0_r1.rs tzc_rom1_r0.rs tzc_rom1_r1.rs tzc_rom_ctrl.rs

uart

data_config.rs sts_urx_abr_prd.rs uart_bit_prd.rs uart_fifo_config_0.rs uart_fifo_config_1.rs uart_fifo_rdata.rs uart_fifo_wdata.rs uart_int_clear.rs uart_int_en.rs uart_int_mask.rs uart_int_sts.rs uart_status.rs urx_config.rs urx_ir_position.rs urx_rto_timer.rs utx_config.rs utx_ir_position.rs

aon.rs cci.rs cks.rs dma.rs ef_ctrl.rs ef_data_0.rs ef_data_1.rs generic.rs glb.rs gpip.rs hbn.rs i2c.rs ir.rs l1c.rs lib.rs pds.rs pwm.rs rf.rs sec_dbg.rs sec_eng.rs sf_ctrl.rs spi.rs timer.rs tzc_nsec.rs tzc_sec.rs uart.rs

bl602_rust_guide

embedded_hal

blocking

delay.rs i2c.rs mod.rs rng.rs serial.rs spi.rs

adc.rs capture.rs digital.rs fmt.rs lib.rs prelude.rs pwm.rs qei.rs rng.rs serial.rs spi.rs timer.rs watchdog.rs

embedded_time

clock.rs duration.rs fixed_point.rs fraction.rs instant.rs lib.rs rate.rs time_int.rs timer.rs

nb

num

num_complex

cast.rs lib.rs pow.rs

num_integer

average.rs lib.rs roots.rs

num_iter

num_rational

num_traits

ops

checked.rs inv.rs mod.rs mul_add.rs overflowing.rs saturating.rs wrapping.rs

bounds.rs cast.rs float.rs identities.rs int.rs lib.rs macros.rs pow.rs sign.rs

panic_halt

r0

riscv

riscv_rt

vcell

//! mideleg register

use bit_field::BitField;

/// mideleg register
#[derive(Clone, Copy, Debug)]
pub struct Mideleg {
    bits: usize,
}

impl Mideleg {
    /// Returns the contents of the register as raw bits
    #[inline]
    pub fn bits(&self) -> usize {
        self.bits
    }

    /// User Software Interrupt Enable
    #[inline]
    pub fn usoft(&self) -> bool {
        self.bits.get_bit(0)
    }

    /// Supervisor Software Interrupt Enable
    #[inline]
    pub fn ssoft(&self) -> bool {
        self.bits.get_bit(1)
    }

    /// User Timer Interrupt Enable
    #[inline]
    pub fn utimer(&self) -> bool {
        self.bits.get_bit(4)
    }

    /// Supervisor Timer Interrupt Enable
    #[inline]
    pub fn stimer(&self) -> bool {
        self.bits.get_bit(5)
    }

    /// User External Interrupt Enable
    #[inline]
    pub fn uext(&self) -> bool {
        self.bits.get_bit(8)
    }

    /// Supervisor External Interrupt Enable
    #[inline]
    pub fn sext(&self) -> bool {
        self.bits.get_bit(9)
    }
}

read_csr_as!(Mideleg, 0x304, __read_mideleg);
set!(0x303, __set_mideleg);
clear!(0x303, __clear_mideleg);

set_clear_csr!(
    /// User Software Interrupt Pending
    , set_usoft, clear_usoft, 1 << 0);
set_clear_csr!(
    /// Supervisor Software Interrupt Pending
    , set_ssoft, clear_ssoft, 1 << 1);
set_clear_csr!(
    /// User Timer Interrupt Pending
    , set_utimer, clear_utimer, 1 << 4);
set_clear_csr!(
    /// Supervisor Timer Interrupt Pending
    , set_stimer, clear_stimer, 1 << 5);
set_clear_csr!(
    /// User External Interrupt Pending
    , set_uext, clear_uext, 1 << 8);
set_clear_csr!(
    /// Supervisor External Interrupt Pending
    , set_sext, clear_sext, 1 << 9);

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