Files
bare_metal
bit_field
bl602_hal
bl602_pac
aon
cci
cks
dma
ef_ctrl
ef_data_0
ef_data_1
glb
gpip
hbn
i2c
ir
l1c
pds
pwm
rf
adda1.rsadda2.rsadda_reg_ctrl_hw.rscip.rsdfe_ctrl_0.rsdfe_ctrl_1.rsdfe_ctrl_10.rsdfe_ctrl_11.rsdfe_ctrl_12.rsdfe_ctrl_13.rsdfe_ctrl_14.rsdfe_ctrl_15.rsdfe_ctrl_16.rsdfe_ctrl_17.rsdfe_ctrl_18.rsdfe_ctrl_2.rsdfe_ctrl_3.rsdfe_ctrl_4.rsdfe_ctrl_5.rsdfe_ctrl_6.rsdfe_ctrl_7.rsdfe_ctrl_8.rsdfe_ctrl_9.rsfbdv.rslna.rslna_ctrl_hw_mux.rslo.rslo_cal_ctrl_hw1.rslo_cal_ctrl_hw10.rslo_cal_ctrl_hw11.rslo_cal_ctrl_hw2.rslo_cal_ctrl_hw3.rslo_cal_ctrl_hw4.rslo_cal_ctrl_hw5.rslo_cal_ctrl_hw6.rslo_cal_ctrl_hw7.rslo_cal_ctrl_hw8.rslo_cal_ctrl_hw9.rslo_reg_ctrl_hw1.rslo_sdm_ctrl_hw1.rslo_sdm_ctrl_hw2.rslo_sdm_ctrl_hw3.rslo_sdm_ctrl_hw4.rslo_sdm_ctrl_hw5.rslo_sdm_ctrl_hw6.rslo_sdm_ctrl_hw7.rslo_sdm_ctrl_hw8.rslodist.rspa1.rspa2.rspa_reg_ctrl_hw1.rspa_reg_ctrl_hw2.rspa_reg_wifi_ctrl_hw.rspfdcp.rspmip_mv2aon.rsppu_ctrl_hw.rspucr1.rspucr1_hw.rspucr2.rspucr2_hw.rspud_ctrl_hw.rsrbb1.rsrbb2.rsrbb3.rsrbb4.rsrbb_bw_ctrl_hw.rsrbb_gain_index1.rsrbb_gain_index2.rsrbb_gain_index3.rsrbb_gain_index4.rsrbb_gain_index5.rsrf_base_ctrl1.rsrf_base_ctrl2.rsrf_data_temp_0.rsrf_data_temp_1.rsrf_data_temp_2.rsrf_data_temp_3.rsrf_fsm_ctrl0.rsrf_fsm_ctrl1.rsrf_fsm_ctrl2.rsrf_fsm_ctrl_hw.rsrf_fsm_ctrl_sw.rsrf_ical_ctrl0.rsrf_ical_ctrl1.rsrf_ical_ctrl2.rsrf_pkdet_ctrl0.rsrf_resv_reg_0.rsrf_resv_reg_1.rsrf_resv_reg_2.rsrf_rev.rsrf_sram_ctrl0.rsrf_sram_ctrl1.rsrf_sram_ctrl2.rsrf_sram_ctrl3.rsrf_sram_ctrl4.rsrf_sram_ctrl5.rsrf_sram_ctrl6.rsrfcal_ctrlen.rsrfcal_stateen.rsrfcal_status.rsrfcal_status2.rsrfctrl_hw_en.rsrfif_dfe_ctrl0.rsrfif_dig_ctrl.rsrfif_test_read.rsrmxgm.rsrosdac_ctrl_hw1.rsrosdac_ctrl_hw2.rsrrf_gain_index1.rsrrf_gain_index2.rsrxiq_ctrl_hw1.rsrxiq_ctrl_hw2.rsrxiq_ctrl_hw3.rsrxiq_ctrl_hw4.rssaradc_resv.rssdm1.rssdm2.rssdm3.rssingen_ctrl0.rssingen_ctrl1.rssingen_ctrl2.rssingen_ctrl3.rssingen_ctrl4.rstbb.rstbb_gain_index1.rstbb_gain_index2.rstbb_gain_index3.rstbb_gain_index4.rstemp_comp.rsten_ac.rsten_dc.rsten_dig.rstmx.rstosdac_ctrl_hw1.rstosdac_ctrl_hw2.rstosdac_ctrl_hw3.rstosdac_ctrl_hw4.rstrx_gain1.rstrx_gain_hw.rstx_iq_gain_hw0.rstx_iq_gain_hw1.rstx_iq_gain_hw2.rstx_iq_gain_hw3.rstx_iq_gain_hw4.rstx_iq_gain_hw5.rstx_iq_gain_hw6.rstx_iq_gain_hw7.rsvco1.rsvco2.rsvco3.rsvco4.rs
sec_dbg
sec_eng
se_aes_0_ctrl.rsse_aes_0_ctrl_prot.rsse_aes_0_endian.rsse_aes_0_iv_0.rsse_aes_0_iv_1.rsse_aes_0_iv_2.rsse_aes_0_iv_3.rsse_aes_0_key_0.rsse_aes_0_key_1.rsse_aes_0_key_2.rsse_aes_0_key_3.rsse_aes_0_key_4.rsse_aes_0_key_5.rsse_aes_0_key_6.rsse_aes_0_key_7.rsse_aes_0_key_sel_0.rsse_aes_0_key_sel_1.rsse_aes_0_link.rsse_aes_0_mda.rsse_aes_0_msa.rsse_aes_0_sboot.rsse_aes_0_status.rsse_cdet_0_ctrl_0.rsse_cdet_0_ctrl_1.rsse_cdet_0_ctrl_prot.rsse_ctrl_prot_rd.rsse_ctrl_reserved_0.rsse_ctrl_reserved_1.rsse_ctrl_reserved_2.rsse_gmac_0_ctrl_0.rsse_gmac_0_ctrl_prot.rsse_gmac_0_lca.rsse_gmac_0_status.rsse_pka_0_ctrl_0.rsse_pka_0_ctrl_1.rsse_pka_0_ctrl_prot.rsse_pka_0_rw.rsse_pka_0_rw_burst.rsse_pka_0_seed.rsse_sha_0_ctrl.rsse_sha_0_ctrl_prot.rsse_sha_0_endian.rsse_sha_0_hash_h_0.rsse_sha_0_hash_h_1.rsse_sha_0_hash_h_2.rsse_sha_0_hash_h_3.rsse_sha_0_hash_h_4.rsse_sha_0_hash_h_5.rsse_sha_0_hash_h_6.rsse_sha_0_hash_h_7.rsse_sha_0_hash_l_0.rsse_sha_0_hash_l_1.rsse_sha_0_hash_l_2.rsse_sha_0_hash_l_3.rsse_sha_0_hash_l_4.rsse_sha_0_hash_l_5.rsse_sha_0_hash_l_6.rsse_sha_0_hash_l_7.rsse_sha_0_link.rsse_sha_0_msa.rsse_sha_0_status.rsse_trng_0_ctrl_0.rsse_trng_0_ctrl_1.rsse_trng_0_ctrl_2.rsse_trng_0_ctrl_3.rsse_trng_0_ctrl_prot.rsse_trng_0_dout_0.rsse_trng_0_dout_1.rsse_trng_0_dout_2.rsse_trng_0_dout_3.rsse_trng_0_dout_4.rsse_trng_0_dout_5.rsse_trng_0_dout_6.rsse_trng_0_dout_7.rsse_trng_0_status.rsse_trng_0_test.rsse_trng_0_test_out_0.rsse_trng_0_test_out_1.rsse_trng_0_test_out_2.rsse_trng_0_test_out_3.rs
sf_ctrl
spi
timer
tzc_nsec
tzc_sec
uart
bl602_rust_guide
embedded_hal
embedded_time
nb
num
num_complex
num_integer
num_iter
num_rational
num_traits
panic_halt
r0
riscv
riscv_rt
vcell
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#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
    #[doc = "0x00 - l1c_config."]
    pub l1c_config: crate::Reg<l1c_config::L1C_CONFIG_SPEC>,
    #[doc = "0x04 - hit_cnt_lsb."]
    pub hit_cnt_lsb: crate::Reg<hit_cnt_lsb::HIT_CNT_LSB_SPEC>,
    #[doc = "0x08 - hit_cnt_msb."]
    pub hit_cnt_msb: crate::Reg<hit_cnt_msb::HIT_CNT_MSB_SPEC>,
    #[doc = "0x0c - miss_cnt."]
    pub miss_cnt: crate::Reg<miss_cnt::MISS_CNT_SPEC>,
    #[doc = "0x10 - l1c_range."]
    pub l1c_range: crate::Reg<l1c_range::L1C_RANGE_SPEC>,
    _reserved5: [u8; 492usize],
    #[doc = "0x200 - l1c_bmx_err_addr_en."]
    pub l1c_bmx_err_addr_en: crate::Reg<l1c_bmx_err_addr_en::L1C_BMX_ERR_ADDR_EN_SPEC>,
    #[doc = "0x204 - l1c_bmx_err_addr."]
    pub l1c_bmx_err_addr: crate::Reg<l1c_bmx_err_addr::L1C_BMX_ERR_ADDR_SPEC>,
    #[doc = "0x208 - irom1_misr_dataout_0."]
    pub irom1_misr_dataout_0: crate::Reg<irom1_misr_dataout_0::IROM1_MISR_DATAOUT_0_SPEC>,
    #[doc = "0x20c - irom1_misr_dataout_1."]
    pub irom1_misr_dataout_1: crate::Reg<irom1_misr_dataout_1::IROM1_MISR_DATAOUT_1_SPEC>,
    #[doc = "0x210 - cpu_clk_gate."]
    pub cpu_clk_gate: crate::Reg<cpu_clk_gate::CPU_CLK_GATE_SPEC>,
}
#[doc = "l1c_config register accessor: an alias for `Reg<L1C_CONFIG_SPEC>`"]
pub type L1C_CONFIG = crate::Reg<l1c_config::L1C_CONFIG_SPEC>;
#[doc = "l1c_config."]
pub mod l1c_config;
#[doc = "hit_cnt_lsb register accessor: an alias for `Reg<HIT_CNT_LSB_SPEC>`"]
pub type HIT_CNT_LSB = crate::Reg<hit_cnt_lsb::HIT_CNT_LSB_SPEC>;
#[doc = "hit_cnt_lsb."]
pub mod hit_cnt_lsb;
#[doc = "hit_cnt_msb register accessor: an alias for `Reg<HIT_CNT_MSB_SPEC>`"]
pub type HIT_CNT_MSB = crate::Reg<hit_cnt_msb::HIT_CNT_MSB_SPEC>;
#[doc = "hit_cnt_msb."]
pub mod hit_cnt_msb;
#[doc = "miss_cnt register accessor: an alias for `Reg<MISS_CNT_SPEC>`"]
pub type MISS_CNT = crate::Reg<miss_cnt::MISS_CNT_SPEC>;
#[doc = "miss_cnt."]
pub mod miss_cnt;
#[doc = "l1c_range register accessor: an alias for `Reg<L1C_RANGE_SPEC>`"]
pub type L1C_RANGE = crate::Reg<l1c_range::L1C_RANGE_SPEC>;
#[doc = "l1c_range."]
pub mod l1c_range;
#[doc = "l1c_bmx_err_addr_en register accessor: an alias for `Reg<L1C_BMX_ERR_ADDR_EN_SPEC>`"]
pub type L1C_BMX_ERR_ADDR_EN = crate::Reg<l1c_bmx_err_addr_en::L1C_BMX_ERR_ADDR_EN_SPEC>;
#[doc = "l1c_bmx_err_addr_en."]
pub mod l1c_bmx_err_addr_en;
#[doc = "l1c_bmx_err_addr register accessor: an alias for `Reg<L1C_BMX_ERR_ADDR_SPEC>`"]
pub type L1C_BMX_ERR_ADDR = crate::Reg<l1c_bmx_err_addr::L1C_BMX_ERR_ADDR_SPEC>;
#[doc = "l1c_bmx_err_addr."]
pub mod l1c_bmx_err_addr;
#[doc = "irom1_misr_dataout_0 register accessor: an alias for `Reg<IROM1_MISR_DATAOUT_0_SPEC>`"]
pub type IROM1_MISR_DATAOUT_0 = crate::Reg<irom1_misr_dataout_0::IROM1_MISR_DATAOUT_0_SPEC>;
#[doc = "irom1_misr_dataout_0."]
pub mod irom1_misr_dataout_0;
#[doc = "irom1_misr_dataout_1 register accessor: an alias for `Reg<IROM1_MISR_DATAOUT_1_SPEC>`"]
pub type IROM1_MISR_DATAOUT_1 = crate::Reg<irom1_misr_dataout_1::IROM1_MISR_DATAOUT_1_SPEC>;
#[doc = "irom1_misr_dataout_1."]
pub mod irom1_misr_dataout_1;
#[doc = "cpu_clk_gate register accessor: an alias for `Reg<CPU_CLK_GATE_SPEC>`"]
pub type CPU_CLK_GATE = crate::Reg<cpu_clk_gate::CPU_CLK_GATE_SPEC>;
#[doc = "cpu_clk_gate."]
pub mod cpu_clk_gate;