Files
bare_metal
bit_field
bl602_hal
bl602_pac
aon
cci
cks
dma
ef_ctrl
ef_data_0
ef_data_1
glb
gpip
hbn
i2c
ir
l1c
pds
pwm
rf
adda1.rsadda2.rsadda_reg_ctrl_hw.rscip.rsdfe_ctrl_0.rsdfe_ctrl_1.rsdfe_ctrl_10.rsdfe_ctrl_11.rsdfe_ctrl_12.rsdfe_ctrl_13.rsdfe_ctrl_14.rsdfe_ctrl_15.rsdfe_ctrl_16.rsdfe_ctrl_17.rsdfe_ctrl_18.rsdfe_ctrl_2.rsdfe_ctrl_3.rsdfe_ctrl_4.rsdfe_ctrl_5.rsdfe_ctrl_6.rsdfe_ctrl_7.rsdfe_ctrl_8.rsdfe_ctrl_9.rsfbdv.rslna.rslna_ctrl_hw_mux.rslo.rslo_cal_ctrl_hw1.rslo_cal_ctrl_hw10.rslo_cal_ctrl_hw11.rslo_cal_ctrl_hw2.rslo_cal_ctrl_hw3.rslo_cal_ctrl_hw4.rslo_cal_ctrl_hw5.rslo_cal_ctrl_hw6.rslo_cal_ctrl_hw7.rslo_cal_ctrl_hw8.rslo_cal_ctrl_hw9.rslo_reg_ctrl_hw1.rslo_sdm_ctrl_hw1.rslo_sdm_ctrl_hw2.rslo_sdm_ctrl_hw3.rslo_sdm_ctrl_hw4.rslo_sdm_ctrl_hw5.rslo_sdm_ctrl_hw6.rslo_sdm_ctrl_hw7.rslo_sdm_ctrl_hw8.rslodist.rspa1.rspa2.rspa_reg_ctrl_hw1.rspa_reg_ctrl_hw2.rspa_reg_wifi_ctrl_hw.rspfdcp.rspmip_mv2aon.rsppu_ctrl_hw.rspucr1.rspucr1_hw.rspucr2.rspucr2_hw.rspud_ctrl_hw.rsrbb1.rsrbb2.rsrbb3.rsrbb4.rsrbb_bw_ctrl_hw.rsrbb_gain_index1.rsrbb_gain_index2.rsrbb_gain_index3.rsrbb_gain_index4.rsrbb_gain_index5.rsrf_base_ctrl1.rsrf_base_ctrl2.rsrf_data_temp_0.rsrf_data_temp_1.rsrf_data_temp_2.rsrf_data_temp_3.rsrf_fsm_ctrl0.rsrf_fsm_ctrl1.rsrf_fsm_ctrl2.rsrf_fsm_ctrl_hw.rsrf_fsm_ctrl_sw.rsrf_ical_ctrl0.rsrf_ical_ctrl1.rsrf_ical_ctrl2.rsrf_pkdet_ctrl0.rsrf_resv_reg_0.rsrf_resv_reg_1.rsrf_resv_reg_2.rsrf_rev.rsrf_sram_ctrl0.rsrf_sram_ctrl1.rsrf_sram_ctrl2.rsrf_sram_ctrl3.rsrf_sram_ctrl4.rsrf_sram_ctrl5.rsrf_sram_ctrl6.rsrfcal_ctrlen.rsrfcal_stateen.rsrfcal_status.rsrfcal_status2.rsrfctrl_hw_en.rsrfif_dfe_ctrl0.rsrfif_dig_ctrl.rsrfif_test_read.rsrmxgm.rsrosdac_ctrl_hw1.rsrosdac_ctrl_hw2.rsrrf_gain_index1.rsrrf_gain_index2.rsrxiq_ctrl_hw1.rsrxiq_ctrl_hw2.rsrxiq_ctrl_hw3.rsrxiq_ctrl_hw4.rssaradc_resv.rssdm1.rssdm2.rssdm3.rssingen_ctrl0.rssingen_ctrl1.rssingen_ctrl2.rssingen_ctrl3.rssingen_ctrl4.rstbb.rstbb_gain_index1.rstbb_gain_index2.rstbb_gain_index3.rstbb_gain_index4.rstemp_comp.rsten_ac.rsten_dc.rsten_dig.rstmx.rstosdac_ctrl_hw1.rstosdac_ctrl_hw2.rstosdac_ctrl_hw3.rstosdac_ctrl_hw4.rstrx_gain1.rstrx_gain_hw.rstx_iq_gain_hw0.rstx_iq_gain_hw1.rstx_iq_gain_hw2.rstx_iq_gain_hw3.rstx_iq_gain_hw4.rstx_iq_gain_hw5.rstx_iq_gain_hw6.rstx_iq_gain_hw7.rsvco1.rsvco2.rsvco3.rsvco4.rs
sec_dbg
sec_eng
se_aes_0_ctrl.rsse_aes_0_ctrl_prot.rsse_aes_0_endian.rsse_aes_0_iv_0.rsse_aes_0_iv_1.rsse_aes_0_iv_2.rsse_aes_0_iv_3.rsse_aes_0_key_0.rsse_aes_0_key_1.rsse_aes_0_key_2.rsse_aes_0_key_3.rsse_aes_0_key_4.rsse_aes_0_key_5.rsse_aes_0_key_6.rsse_aes_0_key_7.rsse_aes_0_key_sel_0.rsse_aes_0_key_sel_1.rsse_aes_0_link.rsse_aes_0_mda.rsse_aes_0_msa.rsse_aes_0_sboot.rsse_aes_0_status.rsse_cdet_0_ctrl_0.rsse_cdet_0_ctrl_1.rsse_cdet_0_ctrl_prot.rsse_ctrl_prot_rd.rsse_ctrl_reserved_0.rsse_ctrl_reserved_1.rsse_ctrl_reserved_2.rsse_gmac_0_ctrl_0.rsse_gmac_0_ctrl_prot.rsse_gmac_0_lca.rsse_gmac_0_status.rsse_pka_0_ctrl_0.rsse_pka_0_ctrl_1.rsse_pka_0_ctrl_prot.rsse_pka_0_rw.rsse_pka_0_rw_burst.rsse_pka_0_seed.rsse_sha_0_ctrl.rsse_sha_0_ctrl_prot.rsse_sha_0_endian.rsse_sha_0_hash_h_0.rsse_sha_0_hash_h_1.rsse_sha_0_hash_h_2.rsse_sha_0_hash_h_3.rsse_sha_0_hash_h_4.rsse_sha_0_hash_h_5.rsse_sha_0_hash_h_6.rsse_sha_0_hash_h_7.rsse_sha_0_hash_l_0.rsse_sha_0_hash_l_1.rsse_sha_0_hash_l_2.rsse_sha_0_hash_l_3.rsse_sha_0_hash_l_4.rsse_sha_0_hash_l_5.rsse_sha_0_hash_l_6.rsse_sha_0_hash_l_7.rsse_sha_0_link.rsse_sha_0_msa.rsse_sha_0_status.rsse_trng_0_ctrl_0.rsse_trng_0_ctrl_1.rsse_trng_0_ctrl_2.rsse_trng_0_ctrl_3.rsse_trng_0_ctrl_prot.rsse_trng_0_dout_0.rsse_trng_0_dout_1.rsse_trng_0_dout_2.rsse_trng_0_dout_3.rsse_trng_0_dout_4.rsse_trng_0_dout_5.rsse_trng_0_dout_6.rsse_trng_0_dout_7.rsse_trng_0_status.rsse_trng_0_test.rsse_trng_0_test_out_0.rsse_trng_0_test_out_1.rsse_trng_0_test_out_2.rsse_trng_0_test_out_3.rs
sf_ctrl
spi
timer
tzc_nsec
tzc_sec
uart
bl602_rust_guide
embedded_hal
embedded_time
nb
num
num_complex
num_integer
num_iter
num_rational
num_traits
panic_halt
r0
riscv
riscv_rt
vcell
  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
    #[doc = "0x00 - HBN_CTL."]
    pub hbn_ctl: crate::Reg<hbn_ctl::HBN_CTL_SPEC>,
    #[doc = "0x04 - HBN_TIME_L."]
    pub hbn_time_l: crate::Reg<hbn_time_l::HBN_TIME_L_SPEC>,
    #[doc = "0x08 - HBN_TIME_H."]
    pub hbn_time_h: crate::Reg<hbn_time_h::HBN_TIME_H_SPEC>,
    #[doc = "0x0c - RTC_TIME_L."]
    pub rtc_time_l: crate::Reg<rtc_time_l::RTC_TIME_L_SPEC>,
    #[doc = "0x10 - RTC_TIME_H."]
    pub rtc_time_h: crate::Reg<rtc_time_h::RTC_TIME_H_SPEC>,
    #[doc = "0x14 - HBN_IRQ_MODE."]
    pub hbn_irq_mode: crate::Reg<hbn_irq_mode::HBN_IRQ_MODE_SPEC>,
    #[doc = "0x18 - HBN_IRQ_STAT."]
    pub hbn_irq_stat: crate::Reg<hbn_irq_stat::HBN_IRQ_STAT_SPEC>,
    #[doc = "0x1c - HBN_IRQ_CLR."]
    pub hbn_irq_clr: crate::Reg<hbn_irq_clr::HBN_IRQ_CLR_SPEC>,
    #[doc = "0x20 - HBN_PIR_CFG."]
    pub hbn_pir_cfg: crate::Reg<hbn_pir_cfg::HBN_PIR_CFG_SPEC>,
    #[doc = "0x24 - HBN_PIR_VTH."]
    pub hbn_pir_vth: crate::Reg<hbn_pir_vth::HBN_PIR_VTH_SPEC>,
    #[doc = "0x28 - HBN_PIR_INTERVAL."]
    pub hbn_pir_interval: crate::Reg<hbn_pir_interval::HBN_PIR_INTERVAL_SPEC>,
    #[doc = "0x2c - HBN_BOR_CFG."]
    pub hbn_bor_cfg: crate::Reg<hbn_bor_cfg::HBN_BOR_CFG_SPEC>,
    #[doc = "0x30 - HBN_GLB."]
    pub hbn_glb: crate::Reg<hbn_glb::HBN_GLB_SPEC>,
    #[doc = "0x34 - HBN_SRAM."]
    pub hbn_sram: crate::Reg<hbn_sram::HBN_SRAM_SPEC>,
    _reserved14: [u8; 200usize],
    #[doc = "0x100 - HBN_RSV0."]
    pub hbn_rsv0: crate::Reg<hbn_rsv0::HBN_RSV0_SPEC>,
    #[doc = "0x104 - HBN_RSV1."]
    pub hbn_rsv1: crate::Reg<hbn_rsv1::HBN_RSV1_SPEC>,
    #[doc = "0x108 - HBN_RSV2."]
    pub hbn_rsv2: crate::Reg<hbn_rsv2::HBN_RSV2_SPEC>,
    #[doc = "0x10c - HBN_RSV3."]
    pub hbn_rsv3: crate::Reg<hbn_rsv3::HBN_RSV3_SPEC>,
    _reserved18: [u8; 240usize],
    #[doc = "0x200 - rc32k_ctrl0."]
    pub rc32k_ctrl0: crate::Reg<rc32k_ctrl0::RC32K_CTRL0_SPEC>,
    #[doc = "0x204 - xtal32k."]
    pub xtal32k: crate::Reg<xtal32k::XTAL32K_SPEC>,
}
#[doc = "HBN_CTL register accessor: an alias for `Reg<HBN_CTL_SPEC>`"]
pub type HBN_CTL = crate::Reg<hbn_ctl::HBN_CTL_SPEC>;
#[doc = "HBN_CTL."]
pub mod hbn_ctl;
#[doc = "HBN_TIME_L register accessor: an alias for `Reg<HBN_TIME_L_SPEC>`"]
pub type HBN_TIME_L = crate::Reg<hbn_time_l::HBN_TIME_L_SPEC>;
#[doc = "HBN_TIME_L."]
pub mod hbn_time_l;
#[doc = "HBN_TIME_H register accessor: an alias for `Reg<HBN_TIME_H_SPEC>`"]
pub type HBN_TIME_H = crate::Reg<hbn_time_h::HBN_TIME_H_SPEC>;
#[doc = "HBN_TIME_H."]
pub mod hbn_time_h;
#[doc = "RTC_TIME_L register accessor: an alias for `Reg<RTC_TIME_L_SPEC>`"]
pub type RTC_TIME_L = crate::Reg<rtc_time_l::RTC_TIME_L_SPEC>;
#[doc = "RTC_TIME_L."]
pub mod rtc_time_l;
#[doc = "RTC_TIME_H register accessor: an alias for `Reg<RTC_TIME_H_SPEC>`"]
pub type RTC_TIME_H = crate::Reg<rtc_time_h::RTC_TIME_H_SPEC>;
#[doc = "RTC_TIME_H."]
pub mod rtc_time_h;
#[doc = "HBN_IRQ_MODE register accessor: an alias for `Reg<HBN_IRQ_MODE_SPEC>`"]
pub type HBN_IRQ_MODE = crate::Reg<hbn_irq_mode::HBN_IRQ_MODE_SPEC>;
#[doc = "HBN_IRQ_MODE."]
pub mod hbn_irq_mode;
#[doc = "HBN_IRQ_STAT register accessor: an alias for `Reg<HBN_IRQ_STAT_SPEC>`"]
pub type HBN_IRQ_STAT = crate::Reg<hbn_irq_stat::HBN_IRQ_STAT_SPEC>;
#[doc = "HBN_IRQ_STAT."]
pub mod hbn_irq_stat;
#[doc = "HBN_IRQ_CLR register accessor: an alias for `Reg<HBN_IRQ_CLR_SPEC>`"]
pub type HBN_IRQ_CLR = crate::Reg<hbn_irq_clr::HBN_IRQ_CLR_SPEC>;
#[doc = "HBN_IRQ_CLR."]
pub mod hbn_irq_clr;
#[doc = "HBN_PIR_CFG register accessor: an alias for `Reg<HBN_PIR_CFG_SPEC>`"]
pub type HBN_PIR_CFG = crate::Reg<hbn_pir_cfg::HBN_PIR_CFG_SPEC>;
#[doc = "HBN_PIR_CFG."]
pub mod hbn_pir_cfg;
#[doc = "HBN_PIR_VTH register accessor: an alias for `Reg<HBN_PIR_VTH_SPEC>`"]
pub type HBN_PIR_VTH = crate::Reg<hbn_pir_vth::HBN_PIR_VTH_SPEC>;
#[doc = "HBN_PIR_VTH."]
pub mod hbn_pir_vth;
#[doc = "HBN_PIR_INTERVAL register accessor: an alias for `Reg<HBN_PIR_INTERVAL_SPEC>`"]
pub type HBN_PIR_INTERVAL = crate::Reg<hbn_pir_interval::HBN_PIR_INTERVAL_SPEC>;
#[doc = "HBN_PIR_INTERVAL."]
pub mod hbn_pir_interval;
#[doc = "HBN_BOR_CFG register accessor: an alias for `Reg<HBN_BOR_CFG_SPEC>`"]
pub type HBN_BOR_CFG = crate::Reg<hbn_bor_cfg::HBN_BOR_CFG_SPEC>;
#[doc = "HBN_BOR_CFG."]
pub mod hbn_bor_cfg;
#[doc = "HBN_GLB register accessor: an alias for `Reg<HBN_GLB_SPEC>`"]
pub type HBN_GLB = crate::Reg<hbn_glb::HBN_GLB_SPEC>;
#[doc = "HBN_GLB."]
pub mod hbn_glb;
#[doc = "HBN_SRAM register accessor: an alias for `Reg<HBN_SRAM_SPEC>`"]
pub type HBN_SRAM = crate::Reg<hbn_sram::HBN_SRAM_SPEC>;
#[doc = "HBN_SRAM."]
pub mod hbn_sram;
#[doc = "HBN_RSV0 register accessor: an alias for `Reg<HBN_RSV0_SPEC>`"]
pub type HBN_RSV0 = crate::Reg<hbn_rsv0::HBN_RSV0_SPEC>;
#[doc = "HBN_RSV0."]
pub mod hbn_rsv0;
#[doc = "HBN_RSV1 register accessor: an alias for `Reg<HBN_RSV1_SPEC>`"]
pub type HBN_RSV1 = crate::Reg<hbn_rsv1::HBN_RSV1_SPEC>;
#[doc = "HBN_RSV1."]
pub mod hbn_rsv1;
#[doc = "HBN_RSV2 register accessor: an alias for `Reg<HBN_RSV2_SPEC>`"]
pub type HBN_RSV2 = crate::Reg<hbn_rsv2::HBN_RSV2_SPEC>;
#[doc = "HBN_RSV2."]
pub mod hbn_rsv2;
#[doc = "HBN_RSV3 register accessor: an alias for `Reg<HBN_RSV3_SPEC>`"]
pub type HBN_RSV3 = crate::Reg<hbn_rsv3::HBN_RSV3_SPEC>;
#[doc = "HBN_RSV3."]
pub mod hbn_rsv3;
#[doc = "rc32k_ctrl0 register accessor: an alias for `Reg<RC32K_CTRL0_SPEC>`"]
pub type RC32K_CTRL0 = crate::Reg<rc32k_ctrl0::RC32K_CTRL0_SPEC>;
#[doc = "rc32k_ctrl0."]
pub mod rc32k_ctrl0;
#[doc = "xtal32k register accessor: an alias for `Reg<XTAL32K_SPEC>`"]
pub type XTAL32K = crate::Reg<xtal32k::XTAL32K_SPEC>;
#[doc = "xtal32k."]
pub mod xtal32k;