Files
bare_metal
bit_field
bl602_hal
bl602_pac
aon
cci
cks
dma
ef_ctrl
ef_data_0
ef_data_1
glb
gpip
hbn
i2c
ir
l1c
pds
pwm
rf
adda1.rsadda2.rsadda_reg_ctrl_hw.rscip.rsdfe_ctrl_0.rsdfe_ctrl_1.rsdfe_ctrl_10.rsdfe_ctrl_11.rsdfe_ctrl_12.rsdfe_ctrl_13.rsdfe_ctrl_14.rsdfe_ctrl_15.rsdfe_ctrl_16.rsdfe_ctrl_17.rsdfe_ctrl_18.rsdfe_ctrl_2.rsdfe_ctrl_3.rsdfe_ctrl_4.rsdfe_ctrl_5.rsdfe_ctrl_6.rsdfe_ctrl_7.rsdfe_ctrl_8.rsdfe_ctrl_9.rsfbdv.rslna.rslna_ctrl_hw_mux.rslo.rslo_cal_ctrl_hw1.rslo_cal_ctrl_hw10.rslo_cal_ctrl_hw11.rslo_cal_ctrl_hw2.rslo_cal_ctrl_hw3.rslo_cal_ctrl_hw4.rslo_cal_ctrl_hw5.rslo_cal_ctrl_hw6.rslo_cal_ctrl_hw7.rslo_cal_ctrl_hw8.rslo_cal_ctrl_hw9.rslo_reg_ctrl_hw1.rslo_sdm_ctrl_hw1.rslo_sdm_ctrl_hw2.rslo_sdm_ctrl_hw3.rslo_sdm_ctrl_hw4.rslo_sdm_ctrl_hw5.rslo_sdm_ctrl_hw6.rslo_sdm_ctrl_hw7.rslo_sdm_ctrl_hw8.rslodist.rspa1.rspa2.rspa_reg_ctrl_hw1.rspa_reg_ctrl_hw2.rspa_reg_wifi_ctrl_hw.rspfdcp.rspmip_mv2aon.rsppu_ctrl_hw.rspucr1.rspucr1_hw.rspucr2.rspucr2_hw.rspud_ctrl_hw.rsrbb1.rsrbb2.rsrbb3.rsrbb4.rsrbb_bw_ctrl_hw.rsrbb_gain_index1.rsrbb_gain_index2.rsrbb_gain_index3.rsrbb_gain_index4.rsrbb_gain_index5.rsrf_base_ctrl1.rsrf_base_ctrl2.rsrf_data_temp_0.rsrf_data_temp_1.rsrf_data_temp_2.rsrf_data_temp_3.rsrf_fsm_ctrl0.rsrf_fsm_ctrl1.rsrf_fsm_ctrl2.rsrf_fsm_ctrl_hw.rsrf_fsm_ctrl_sw.rsrf_ical_ctrl0.rsrf_ical_ctrl1.rsrf_ical_ctrl2.rsrf_pkdet_ctrl0.rsrf_resv_reg_0.rsrf_resv_reg_1.rsrf_resv_reg_2.rsrf_rev.rsrf_sram_ctrl0.rsrf_sram_ctrl1.rsrf_sram_ctrl2.rsrf_sram_ctrl3.rsrf_sram_ctrl4.rsrf_sram_ctrl5.rsrf_sram_ctrl6.rsrfcal_ctrlen.rsrfcal_stateen.rsrfcal_status.rsrfcal_status2.rsrfctrl_hw_en.rsrfif_dfe_ctrl0.rsrfif_dig_ctrl.rsrfif_test_read.rsrmxgm.rsrosdac_ctrl_hw1.rsrosdac_ctrl_hw2.rsrrf_gain_index1.rsrrf_gain_index2.rsrxiq_ctrl_hw1.rsrxiq_ctrl_hw2.rsrxiq_ctrl_hw3.rsrxiq_ctrl_hw4.rssaradc_resv.rssdm1.rssdm2.rssdm3.rssingen_ctrl0.rssingen_ctrl1.rssingen_ctrl2.rssingen_ctrl3.rssingen_ctrl4.rstbb.rstbb_gain_index1.rstbb_gain_index2.rstbb_gain_index3.rstbb_gain_index4.rstemp_comp.rsten_ac.rsten_dc.rsten_dig.rstmx.rstosdac_ctrl_hw1.rstosdac_ctrl_hw2.rstosdac_ctrl_hw3.rstosdac_ctrl_hw4.rstrx_gain1.rstrx_gain_hw.rstx_iq_gain_hw0.rstx_iq_gain_hw1.rstx_iq_gain_hw2.rstx_iq_gain_hw3.rstx_iq_gain_hw4.rstx_iq_gain_hw5.rstx_iq_gain_hw6.rstx_iq_gain_hw7.rsvco1.rsvco2.rsvco3.rsvco4.rs
sec_dbg
sec_eng
se_aes_0_ctrl.rsse_aes_0_ctrl_prot.rsse_aes_0_endian.rsse_aes_0_iv_0.rsse_aes_0_iv_1.rsse_aes_0_iv_2.rsse_aes_0_iv_3.rsse_aes_0_key_0.rsse_aes_0_key_1.rsse_aes_0_key_2.rsse_aes_0_key_3.rsse_aes_0_key_4.rsse_aes_0_key_5.rsse_aes_0_key_6.rsse_aes_0_key_7.rsse_aes_0_key_sel_0.rsse_aes_0_key_sel_1.rsse_aes_0_link.rsse_aes_0_mda.rsse_aes_0_msa.rsse_aes_0_sboot.rsse_aes_0_status.rsse_cdet_0_ctrl_0.rsse_cdet_0_ctrl_1.rsse_cdet_0_ctrl_prot.rsse_ctrl_prot_rd.rsse_ctrl_reserved_0.rsse_ctrl_reserved_1.rsse_ctrl_reserved_2.rsse_gmac_0_ctrl_0.rsse_gmac_0_ctrl_prot.rsse_gmac_0_lca.rsse_gmac_0_status.rsse_pka_0_ctrl_0.rsse_pka_0_ctrl_1.rsse_pka_0_ctrl_prot.rsse_pka_0_rw.rsse_pka_0_rw_burst.rsse_pka_0_seed.rsse_sha_0_ctrl.rsse_sha_0_ctrl_prot.rsse_sha_0_endian.rsse_sha_0_hash_h_0.rsse_sha_0_hash_h_1.rsse_sha_0_hash_h_2.rsse_sha_0_hash_h_3.rsse_sha_0_hash_h_4.rsse_sha_0_hash_h_5.rsse_sha_0_hash_h_6.rsse_sha_0_hash_h_7.rsse_sha_0_hash_l_0.rsse_sha_0_hash_l_1.rsse_sha_0_hash_l_2.rsse_sha_0_hash_l_3.rsse_sha_0_hash_l_4.rsse_sha_0_hash_l_5.rsse_sha_0_hash_l_6.rsse_sha_0_hash_l_7.rsse_sha_0_link.rsse_sha_0_msa.rsse_sha_0_status.rsse_trng_0_ctrl_0.rsse_trng_0_ctrl_1.rsse_trng_0_ctrl_2.rsse_trng_0_ctrl_3.rsse_trng_0_ctrl_prot.rsse_trng_0_dout_0.rsse_trng_0_dout_1.rsse_trng_0_dout_2.rsse_trng_0_dout_3.rsse_trng_0_dout_4.rsse_trng_0_dout_5.rsse_trng_0_dout_6.rsse_trng_0_dout_7.rsse_trng_0_status.rsse_trng_0_test.rsse_trng_0_test_out_0.rsse_trng_0_test_out_1.rsse_trng_0_test_out_2.rsse_trng_0_test_out_3.rs
sf_ctrl
spi
timer
tzc_nsec
tzc_sec
uart
bl602_rust_guide
embedded_hal
embedded_time
nb
num
num_complex
num_integer
num_iter
num_rational
num_traits
panic_halt
r0
riscv
riscv_rt
vcell
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#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
    #[doc = "0x00 - PDS_CTL."]
    pub pds_ctl: crate::Reg<pds_ctl::PDS_CTL_SPEC>,
    #[doc = "0x04 - PDS_TIME1."]
    pub pds_time1: crate::Reg<pds_time1::PDS_TIME1_SPEC>,
    _reserved2: [u8; 4usize],
    #[doc = "0x0c - PDS_INT."]
    pub pds_int: crate::Reg<pds_int::PDS_INT_SPEC>,
    #[doc = "0x10 - PDS_CTL2."]
    pub pds_ctl2: crate::Reg<pds_ctl2::PDS_CTL2_SPEC>,
    #[doc = "0x14 - PDS_CTL3."]
    pub pds_ctl3: crate::Reg<pds_ctl3::PDS_CTL3_SPEC>,
    #[doc = "0x18 - PDS_CTL4."]
    pub pds_ctl4: crate::Reg<pds_ctl4::PDS_CTL4_SPEC>,
    #[doc = "0x1c - pds_stat."]
    pub pds_stat: crate::Reg<pds_stat::PDS_STAT_SPEC>,
    #[doc = "0x20 - pds_ram1."]
    pub pds_ram1: crate::Reg<pds_ram1::PDS_RAM1_SPEC>,
    _reserved8: [u8; 732usize],
    #[doc = "0x300 - rc32m_ctrl0."]
    pub rc32m_ctrl0: crate::Reg<rc32m_ctrl0::RC32M_CTRL0_SPEC>,
    #[doc = "0x304 - rc32m_ctrl1."]
    pub rc32m_ctrl1: crate::Reg<rc32m_ctrl1::RC32M_CTRL1_SPEC>,
    _reserved10: [u8; 248usize],
    #[doc = "0x400 - pu_rst_clkpll."]
    pub pu_rst_clkpll: crate::Reg<pu_rst_clkpll::PU_RST_CLKPLL_SPEC>,
    #[doc = "0x404 - clkpll_top_ctrl."]
    pub clkpll_top_ctrl: crate::Reg<clkpll_top_ctrl::CLKPLL_TOP_CTRL_SPEC>,
    #[doc = "0x408 - clkpll_cp."]
    pub clkpll_cp: crate::Reg<clkpll_cp::CLKPLL_CP_SPEC>,
    #[doc = "0x40c - clkpll_rz."]
    pub clkpll_rz: crate::Reg<clkpll_rz::CLKPLL_RZ_SPEC>,
    #[doc = "0x410 - clkpll_fbdv."]
    pub clkpll_fbdv: crate::Reg<clkpll_fbdv::CLKPLL_FBDV_SPEC>,
    #[doc = "0x414 - clkpll_vco."]
    pub clkpll_vco: crate::Reg<clkpll_vco::CLKPLL_VCO_SPEC>,
    #[doc = "0x418 - clkpll_sdm."]
    pub clkpll_sdm: crate::Reg<clkpll_sdm::CLKPLL_SDM_SPEC>,
    #[doc = "0x41c - clkpll_output_en."]
    pub clkpll_output_en: crate::Reg<clkpll_output_en::CLKPLL_OUTPUT_EN_SPEC>,
}
#[doc = "PDS_CTL register accessor: an alias for `Reg<PDS_CTL_SPEC>`"]
pub type PDS_CTL = crate::Reg<pds_ctl::PDS_CTL_SPEC>;
#[doc = "PDS_CTL."]
pub mod pds_ctl;
#[doc = "PDS_TIME1 register accessor: an alias for `Reg<PDS_TIME1_SPEC>`"]
pub type PDS_TIME1 = crate::Reg<pds_time1::PDS_TIME1_SPEC>;
#[doc = "PDS_TIME1."]
pub mod pds_time1;
#[doc = "PDS_INT register accessor: an alias for `Reg<PDS_INT_SPEC>`"]
pub type PDS_INT = crate::Reg<pds_int::PDS_INT_SPEC>;
#[doc = "PDS_INT."]
pub mod pds_int;
#[doc = "PDS_CTL2 register accessor: an alias for `Reg<PDS_CTL2_SPEC>`"]
pub type PDS_CTL2 = crate::Reg<pds_ctl2::PDS_CTL2_SPEC>;
#[doc = "PDS_CTL2."]
pub mod pds_ctl2;
#[doc = "PDS_CTL3 register accessor: an alias for `Reg<PDS_CTL3_SPEC>`"]
pub type PDS_CTL3 = crate::Reg<pds_ctl3::PDS_CTL3_SPEC>;
#[doc = "PDS_CTL3."]
pub mod pds_ctl3;
#[doc = "PDS_CTL4 register accessor: an alias for `Reg<PDS_CTL4_SPEC>`"]
pub type PDS_CTL4 = crate::Reg<pds_ctl4::PDS_CTL4_SPEC>;
#[doc = "PDS_CTL4."]
pub mod pds_ctl4;
#[doc = "pds_stat register accessor: an alias for `Reg<PDS_STAT_SPEC>`"]
pub type PDS_STAT = crate::Reg<pds_stat::PDS_STAT_SPEC>;
#[doc = "pds_stat."]
pub mod pds_stat;
#[doc = "pds_ram1 register accessor: an alias for `Reg<PDS_RAM1_SPEC>`"]
pub type PDS_RAM1 = crate::Reg<pds_ram1::PDS_RAM1_SPEC>;
#[doc = "pds_ram1."]
pub mod pds_ram1;
#[doc = "rc32m_ctrl0 register accessor: an alias for `Reg<RC32M_CTRL0_SPEC>`"]
pub type RC32M_CTRL0 = crate::Reg<rc32m_ctrl0::RC32M_CTRL0_SPEC>;
#[doc = "rc32m_ctrl0."]
pub mod rc32m_ctrl0;
#[doc = "rc32m_ctrl1 register accessor: an alias for `Reg<RC32M_CTRL1_SPEC>`"]
pub type RC32M_CTRL1 = crate::Reg<rc32m_ctrl1::RC32M_CTRL1_SPEC>;
#[doc = "rc32m_ctrl1."]
pub mod rc32m_ctrl1;
#[doc = "pu_rst_clkpll register accessor: an alias for `Reg<PU_RST_CLKPLL_SPEC>`"]
pub type PU_RST_CLKPLL = crate::Reg<pu_rst_clkpll::PU_RST_CLKPLL_SPEC>;
#[doc = "pu_rst_clkpll."]
pub mod pu_rst_clkpll;
#[doc = "clkpll_top_ctrl register accessor: an alias for `Reg<CLKPLL_TOP_CTRL_SPEC>`"]
pub type CLKPLL_TOP_CTRL = crate::Reg<clkpll_top_ctrl::CLKPLL_TOP_CTRL_SPEC>;
#[doc = "clkpll_top_ctrl."]
pub mod clkpll_top_ctrl;
#[doc = "clkpll_cp register accessor: an alias for `Reg<CLKPLL_CP_SPEC>`"]
pub type CLKPLL_CP = crate::Reg<clkpll_cp::CLKPLL_CP_SPEC>;
#[doc = "clkpll_cp."]
pub mod clkpll_cp;
#[doc = "clkpll_rz register accessor: an alias for `Reg<CLKPLL_RZ_SPEC>`"]
pub type CLKPLL_RZ = crate::Reg<clkpll_rz::CLKPLL_RZ_SPEC>;
#[doc = "clkpll_rz."]
pub mod clkpll_rz;
#[doc = "clkpll_fbdv register accessor: an alias for `Reg<CLKPLL_FBDV_SPEC>`"]
pub type CLKPLL_FBDV = crate::Reg<clkpll_fbdv::CLKPLL_FBDV_SPEC>;
#[doc = "clkpll_fbdv."]
pub mod clkpll_fbdv;
#[doc = "clkpll_vco register accessor: an alias for `Reg<CLKPLL_VCO_SPEC>`"]
pub type CLKPLL_VCO = crate::Reg<clkpll_vco::CLKPLL_VCO_SPEC>;
#[doc = "clkpll_vco."]
pub mod clkpll_vco;
#[doc = "clkpll_sdm register accessor: an alias for `Reg<CLKPLL_SDM_SPEC>`"]
pub type CLKPLL_SDM = crate::Reg<clkpll_sdm::CLKPLL_SDM_SPEC>;
#[doc = "clkpll_sdm."]
pub mod clkpll_sdm;
#[doc = "clkpll_output_en register accessor: an alias for `Reg<CLKPLL_OUTPUT_EN_SPEC>`"]
pub type CLKPLL_OUTPUT_EN = crate::Reg<clkpll_output_en::CLKPLL_OUTPUT_EN_SPEC>;
#[doc = "clkpll_output_en."]
pub mod clkpll_output_en;