[−][src]Struct bl602_pac::timer::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub tccr: Reg<TCCR_SPEC>,
    pub tmr2_0: Reg<TMR2_0_SPEC>,
    pub tmr2_1: Reg<TMR2_1_SPEC>,
    pub tmr2_2: Reg<TMR2_2_SPEC>,
    pub tmr3_0: Reg<TMR3_0_SPEC>,
    pub tmr3_1: Reg<TMR3_1_SPEC>,
    pub tmr3_2: Reg<TMR3_2_SPEC>,
    pub tcr2: Reg<TCR2_SPEC>,
    pub tcr3: Reg<TCR3_SPEC>,
    pub tmsr2: Reg<TMSR2_SPEC>,
    pub tmsr3: Reg<TMSR3_SPEC>,
    pub tier2: Reg<TIER2_SPEC>,
    pub tier3: Reg<TIER3_SPEC>,
    pub tplvr2: Reg<TPLVR2_SPEC>,
    pub tplvr3: Reg<TPLVR3_SPEC>,
    pub tplcr2: Reg<TPLCR2_SPEC>,
    pub tplcr3: Reg<TPLCR3_SPEC>,
    pub wmer: Reg<WMER_SPEC>,
    pub wmr: Reg<WMR_SPEC>,
    pub wvr: Reg<WVR_SPEC>,
    pub wsr: Reg<WSR_SPEC>,
    pub ticr2: Reg<TICR2_SPEC>,
    pub ticr3: Reg<TICR3_SPEC>,
    pub wicr: Reg<WICR_SPEC>,
    pub tcer: Reg<TCER_SPEC>,
    pub tcmr: Reg<TCMR_SPEC>,
    pub tilr2: Reg<TILR2_SPEC>,
    pub tilr3: Reg<TILR3_SPEC>,
    pub wcr: Reg<WCR_SPEC>,
    pub wfar: Reg<WFAR_SPEC>,
    pub wsar: Reg<WSAR_SPEC>,
    pub tcvwr2: Reg<TCVWR2_SPEC>,
    pub tcvwr3: Reg<TCVWR3_SPEC>,
    pub tcvsyn2: Reg<TCVSYN2_SPEC>,
    pub tcvsyn3: Reg<TCVSYN3_SPEC>,
    pub tcdr: Reg<TCDR_SPEC>,
    // some fields omitted
}

Register block

Fields

tccr: Reg<TCCR_SPEC>

0x00 - TCCR.

tmr2_0: Reg<TMR2_0_SPEC>

0x10 - TMR2_0.

tmr2_1: Reg<TMR2_1_SPEC>

0x14 - TMR2_1.

tmr2_2: Reg<TMR2_2_SPEC>

0x18 - TMR2_2.

tmr3_0: Reg<TMR3_0_SPEC>

0x1c - TMR3_0.

tmr3_1: Reg<TMR3_1_SPEC>

0x20 - TMR3_1.

tmr3_2: Reg<TMR3_2_SPEC>

0x24 - TMR3_2.

tcr2: Reg<TCR2_SPEC>

0x2c - TCR2.

tcr3: Reg<TCR3_SPEC>

0x30 - TCR3.

tmsr2: Reg<TMSR2_SPEC>

0x38 - TMSR2.

tmsr3: Reg<TMSR3_SPEC>

0x3c - TMSR3.

tier2: Reg<TIER2_SPEC>

0x44 - TIER2.

tier3: Reg<TIER3_SPEC>

0x48 - TIER3.

tplvr2: Reg<TPLVR2_SPEC>

0x50 - TPLVR2.

tplvr3: Reg<TPLVR3_SPEC>

0x54 - TPLVR3.

tplcr2: Reg<TPLCR2_SPEC>

0x5c - TPLCR2.

tplcr3: Reg<TPLCR3_SPEC>

0x60 - TPLCR3.

wmer: Reg<WMER_SPEC>

0x64 - WMER.

wmr: Reg<WMR_SPEC>

0x68 - WMR.

wvr: Reg<WVR_SPEC>

0x6c - WVR.

wsr: Reg<WSR_SPEC>

0x70 - WSR.

ticr2: Reg<TICR2_SPEC>

0x78 - TICR2.

ticr3: Reg<TICR3_SPEC>

0x7c - TICR3.

wicr: Reg<WICR_SPEC>

0x80 - WICR.

tcer: Reg<TCER_SPEC>

0x84 - TCER.

tcmr: Reg<TCMR_SPEC>

0x88 - TCMR.

tilr2: Reg<TILR2_SPEC>

0x90 - TILR2.

tilr3: Reg<TILR3_SPEC>

0x94 - TILR3.

wcr: Reg<WCR_SPEC>

0x98 - WCR.

wfar: Reg<WFAR_SPEC>

0x9c - WFAR.

wsar: Reg<WSAR_SPEC>

0xa0 - WSAR.

tcvwr2: Reg<TCVWR2_SPEC>

0xa8 - TCVWR2.

tcvwr3: Reg<TCVWR3_SPEC>

0xac - TCVWR3.

tcvsyn2: Reg<TCVSYN2_SPEC>

0xb4 - TCVSYN2.

tcvsyn3: Reg<TCVSYN3_SPEC>

0xb8 - TCVSYN3.

tcdr: Reg<TCDR_SPEC>

0xbc - TCDR.

Auto Trait Implementations

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, [src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.