[][src]Struct bl602_pac::generic::Reg

pub struct Reg<REG: RegisterSpec> { /* fields omitted */ }

This structure provides volatile access to registers.

Implementations

impl<REG: RegisterSpec> Reg<REG>[src]

pub fn as_ptr(&self) -> *mut REG::Ux[src]

Returns the underlying memory address of register.

This example is not tested
let reg_ptr = periph.reg.as_ptr();

impl<REG: Readable> Reg<REG>[src]

pub fn read(&self) -> REG::Reader[src]

Reads the contents of a Readable register.

You can read the raw contents of a register by using bits:

This example is not tested
let bits = periph.reg.read().bits();

or get the content of a particular field of a register:

This example is not tested
let reader = periph.reg.read();
let bits = reader.field1().bits();
let flag = reader.field2().bit_is_set();

impl<REG: Resettable + Writable> Reg<REG>[src]

pub fn reset(&self)[src]

Writes the reset value to Writable register.

Resets the register to its initial state.

pub fn write<F>(&self, f: F) where
    F: FnOnce(&mut REG::Writer) -> &mut W<REG>, 
[src]

Writes bits to a Writable register.

You can write raw bits into a register:

This example is not tested
periph.reg.write(|w| unsafe { w.bits(rawbits) });

or write only the fields you need:

This example is not tested
periph.reg.write(|w| w
    .field1().bits(newfield1bits)
    .field2().set_bit()
    .field3().variant(VARIANT)
);

In the latter case, other fields will be set to their reset value.

impl<REG: Writable> Reg<REG> where
    REG::Ux: Default
[src]

pub fn write_with_zero<F>(&self, f: F) where
    F: FnOnce(&mut REG::Writer) -> &mut W<REG>, 
[src]

Writes 0 to a Writable register.

Similar to write, but unused bits will contain 0.

impl<REG: Readable + Writable> Reg<REG>[src]

pub fn modify<F>(&self, f: F) where
    F: FnOnce(&REG::Reader, &'w mut REG::Writer) -> &'w mut W<REG>, 
[src]

Modifies the contents of the register by reading and then writing it.

E.g. to do a read-modify-write sequence to change parts of a register:

This example is not tested
periph.reg.modify(|r, w| unsafe { w.bits(
   r.bits() | 3
) });

or

This example is not tested
periph.reg.modify(|_, w| w
    .field1().bits(newfield1bits)
    .field2().set_bit()
    .field3().variant(VARIANT)
);

Other fields will have the value they had before the call to modify.

Trait Implementations

impl<REG: RegisterSpec> Send for Reg<REG> where
    REG::Ux: Send
[src]

Auto Trait Implementations

impl<REG> !Sync for Reg<REG>

impl<REG> Unpin for Reg<REG> where
    REG: Unpin,
    <REG as RegisterSpec>::Ux: Unpin

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.