[][src]Struct bl602_pac::sf_ctrl::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub sf_ctrl_0: Reg<SF_CTRL_0_SPEC>,
    pub sf_ctrl_1: Reg<SF_CTRL_1_SPEC>,
    pub sf_if_sahb_0: Reg<SF_IF_SAHB_0_SPEC>,
    pub sf_if_sahb_1: Reg<SF_IF_SAHB_1_SPEC>,
    pub sf_if_sahb_2: Reg<SF_IF_SAHB_2_SPEC>,
    pub sf_if_iahb_0: Reg<SF_IF_IAHB_0_SPEC>,
    pub sf_if_iahb_1: Reg<SF_IF_IAHB_1_SPEC>,
    pub sf_if_iahb_2: Reg<SF_IF_IAHB_2_SPEC>,
    pub sf_if_status_0: Reg<SF_IF_STATUS_0_SPEC>,
    pub sf_if_status_1: Reg<SF_IF_STATUS_1_SPEC>,
    pub sf_aes: Reg<SF_AES_SPEC>,
    pub sf_ahb2sif_status: Reg<SF_AHB2SIF_STATUS_SPEC>,
    pub sf_if_io_dly_0: Reg<SF_IF_IO_DLY_0_SPEC>,
    pub sf_if_io_dly_1: Reg<SF_IF_IO_DLY_1_SPEC>,
    pub sf_if_io_dly_2: Reg<SF_IF_IO_DLY_2_SPEC>,
    pub sf_if_io_dly_3: Reg<SF_IF_IO_DLY_3_SPEC>,
    pub sf_if_io_dly_4: Reg<SF_IF_IO_DLY_4_SPEC>,
    pub sf_reserved: Reg<SF_RESERVED_SPEC>,
    pub sf2_if_io_dly_0: Reg<SF2_IF_IO_DLY_0_SPEC>,
    pub sf2_if_io_dly_1: Reg<SF2_IF_IO_DLY_1_SPEC>,
    pub sf2_if_io_dly_2: Reg<SF2_IF_IO_DLY_2_SPEC>,
    pub sf2_if_io_dly_3: Reg<SF2_IF_IO_DLY_3_SPEC>,
    pub sf2_if_io_dly_4: Reg<SF2_IF_IO_DLY_4_SPEC>,
    pub sf3_if_io_dly_0: Reg<SF3_IF_IO_DLY_0_SPEC>,
    pub sf3_if_io_dly_1: Reg<SF3_IF_IO_DLY_1_SPEC>,
    pub sf3_if_io_dly_2: Reg<SF3_IF_IO_DLY_2_SPEC>,
    pub sf3_if_io_dly_3: Reg<SF3_IF_IO_DLY_3_SPEC>,
    pub sf3_if_io_dly_4: Reg<SF3_IF_IO_DLY_4_SPEC>,
    pub sf_ctrl_2: Reg<SF_CTRL_2_SPEC>,
    pub sf_ctrl_3: Reg<SF_CTRL_3_SPEC>,
    pub sf_if_iahb_3: Reg<SF_IF_IAHB_3_SPEC>,
    pub sf_if_iahb_4: Reg<SF_IF_IAHB_4_SPEC>,
    pub sf_if_iahb_5: Reg<SF_IF_IAHB_5_SPEC>,
    pub sf_if_iahb_6: Reg<SF_IF_IAHB_6_SPEC>,
    pub sf_if_iahb_7: Reg<SF_IF_IAHB_7_SPEC>,
    pub sf_ctrl_prot_en_rd: Reg<SF_CTRL_PROT_EN_RD_SPEC>,
    pub sf_ctrl_prot_en: Reg<SF_CTRL_PROT_EN_SPEC>,
    pub sf_aes_key_r0_0: Reg<SF_AES_KEY_R0_0_SPEC>,
    pub sf_aes_key_r0_1: Reg<SF_AES_KEY_R0_1_SPEC>,
    pub sf_aes_key_r0_2: Reg<SF_AES_KEY_R0_2_SPEC>,
    pub sf_aes_key_r0_3: Reg<SF_AES_KEY_R0_3_SPEC>,
    pub sf_aes_key_r0_4: Reg<SF_AES_KEY_R0_4_SPEC>,
    pub sf_aes_key_r0_5: Reg<SF_AES_KEY_R0_5_SPEC>,
    pub sf_aes_key_r0_6: Reg<SF_AES_KEY_R0_6_SPEC>,
    pub sf_aes_key_r0_7: Reg<SF_AES_KEY_R0_7_SPEC>,
    pub sf_aes_iv_r0_w0: Reg<SF_AES_IV_R0_W0_SPEC>,
    pub sf_aes_iv_r0_w1: Reg<SF_AES_IV_R0_W1_SPEC>,
    pub sf_aes_iv_r0_w2: Reg<SF_AES_IV_R0_W2_SPEC>,
    pub sf_aes_iv_r0_w3: Reg<SF_AES_IV_R0_W3_SPEC>,
    pub sf_aes_cfg_r0: Reg<SF_AES_CFG_R0_SPEC>,
    pub sf_aes_key_r1_0: Reg<SF_AES_KEY_R1_0_SPEC>,
    pub sf_aes_key_r1_1: Reg<SF_AES_KEY_R1_1_SPEC>,
    pub sf_aes_key_r1_2: Reg<SF_AES_KEY_R1_2_SPEC>,
    pub sf_aes_key_r1_3: Reg<SF_AES_KEY_R1_3_SPEC>,
    pub sf_aes_key_r1_4: Reg<SF_AES_KEY_R1_4_SPEC>,
    pub sf_aes_key_r1_5: Reg<SF_AES_KEY_R1_5_SPEC>,
    pub sf_aes_key_r1_6: Reg<SF_AES_KEY_R1_6_SPEC>,
    pub sf_aes_key_r1_7: Reg<SF_AES_KEY_R1_7_SPEC>,
    pub sf_aes_iv_r1_w0: Reg<SF_AES_IV_R1_W0_SPEC>,
    pub sf_aes_iv_r1_w1: Reg<SF_AES_IV_R1_W1_SPEC>,
    pub sf_aes_iv_r1_w2: Reg<SF_AES_IV_R1_W2_SPEC>,
    pub sf_aes_iv_r1_w3: Reg<SF_AES_IV_R1_W3_SPEC>,
    pub sf_aes_r1: Reg<SF_AES_R1_SPEC>,
    pub sf_aes_key_r2_0: Reg<SF_AES_KEY_R2_0_SPEC>,
    pub sf_aes_key_r2_1: Reg<SF_AES_KEY_R2_1_SPEC>,
    pub sf_aes_key_r2_2: Reg<SF_AES_KEY_R2_2_SPEC>,
    pub sf_aes_key_r2_3: Reg<SF_AES_KEY_R2_3_SPEC>,
    pub sf_aes_key_r2_4: Reg<SF_AES_KEY_R2_4_SPEC>,
    pub sf_aes_key_r2_5: Reg<SF_AES_KEY_R2_5_SPEC>,
    pub sf_aes_key_r2_6: Reg<SF_AES_KEY_R2_6_SPEC>,
    pub sf_aes_key_r2_7: Reg<SF_AES_KEY_R2_7_SPEC>,
    pub sf_aes_iv_r2_w0: Reg<SF_AES_IV_R2_W0_SPEC>,
    pub sf_aes_iv_r2_w1: Reg<SF_AES_IV_R2_W1_SPEC>,
    pub sf_aes_iv_r2_w2: Reg<SF_AES_IV_R2_W2_SPEC>,
    pub sf_aes_iv_r2_w3: Reg<SF_AES_IV_R2_W3_SPEC>,
    pub sf_aes_r2: Reg<SF_AES_R2_SPEC>,
    pub sf_id0_offset: Reg<SF_ID0_OFFSET_SPEC>,
    pub sf_id1_offset: Reg<SF_ID1_OFFSET_SPEC>,
    // some fields omitted
}

Register block

Fields

sf_ctrl_0: Reg<SF_CTRL_0_SPEC>

0x00 - sf_ctrl_0.

sf_ctrl_1: Reg<SF_CTRL_1_SPEC>

0x04 - sf_ctrl_1.

sf_if_sahb_0: Reg<SF_IF_SAHB_0_SPEC>

0x08 - sf_if_sahb_0.

sf_if_sahb_1: Reg<SF_IF_SAHB_1_SPEC>

0x0c - sf_if_sahb_1.

sf_if_sahb_2: Reg<SF_IF_SAHB_2_SPEC>

0x10 - sf_if_sahb_2.

sf_if_iahb_0: Reg<SF_IF_IAHB_0_SPEC>

0x14 - sf_if_iahb_0.

sf_if_iahb_1: Reg<SF_IF_IAHB_1_SPEC>

0x18 - sf_if_iahb_1.

sf_if_iahb_2: Reg<SF_IF_IAHB_2_SPEC>

0x1c - sf_if_iahb_2.

sf_if_status_0: Reg<SF_IF_STATUS_0_SPEC>

0x20 - sf_if_status_0.

sf_if_status_1: Reg<SF_IF_STATUS_1_SPEC>

0x24 - sf_if_status_1.

sf_aes: Reg<SF_AES_SPEC>

0x28 - sf_aes.

sf_ahb2sif_status: Reg<SF_AHB2SIF_STATUS_SPEC>

0x2c - sf_ahb2sif_status.

sf_if_io_dly_0: Reg<SF_IF_IO_DLY_0_SPEC>

0x30 - sf_if_io_dly_0.

sf_if_io_dly_1: Reg<SF_IF_IO_DLY_1_SPEC>

0x34 - sf_if_io_dly_1.

sf_if_io_dly_2: Reg<SF_IF_IO_DLY_2_SPEC>

0x38 - sf_if_io_dly_2.

sf_if_io_dly_3: Reg<SF_IF_IO_DLY_3_SPEC>

0x3c - sf_if_io_dly_3.

sf_if_io_dly_4: Reg<SF_IF_IO_DLY_4_SPEC>

0x40 - sf_if_io_dly_4.

sf_reserved: Reg<SF_RESERVED_SPEC>

0x44 - sf_reserved.

sf2_if_io_dly_0: Reg<SF2_IF_IO_DLY_0_SPEC>

0x48 - sf2_if_io_dly_0.

sf2_if_io_dly_1: Reg<SF2_IF_IO_DLY_1_SPEC>

0x4c - sf2_if_io_dly_1.

sf2_if_io_dly_2: Reg<SF2_IF_IO_DLY_2_SPEC>

0x50 - sf2_if_io_dly_2.

sf2_if_io_dly_3: Reg<SF2_IF_IO_DLY_3_SPEC>

0x54 - sf2_if_io_dly_3.

sf2_if_io_dly_4: Reg<SF2_IF_IO_DLY_4_SPEC>

0x58 - sf2_if_io_dly_4.

sf3_if_io_dly_0: Reg<SF3_IF_IO_DLY_0_SPEC>

0x5c - sf3_if_io_dly_0.

sf3_if_io_dly_1: Reg<SF3_IF_IO_DLY_1_SPEC>

0x60 - sf3_if_io_dly_1.

sf3_if_io_dly_2: Reg<SF3_IF_IO_DLY_2_SPEC>

0x64 - sf3_if_io_dly_2.

sf3_if_io_dly_3: Reg<SF3_IF_IO_DLY_3_SPEC>

0x68 - sf3_if_io_dly_3.

sf3_if_io_dly_4: Reg<SF3_IF_IO_DLY_4_SPEC>

0x6c - sf3_if_io_dly_4.

sf_ctrl_2: Reg<SF_CTRL_2_SPEC>

0x70 - sf_ctrl_2.

sf_ctrl_3: Reg<SF_CTRL_3_SPEC>

0x74 - sf_ctrl_3.

sf_if_iahb_3: Reg<SF_IF_IAHB_3_SPEC>

0x78 - sf_if_iahb_3.

sf_if_iahb_4: Reg<SF_IF_IAHB_4_SPEC>

0x7c - sf_if_iahb_4.

sf_if_iahb_5: Reg<SF_IF_IAHB_5_SPEC>

0x80 - sf_if_iahb_5.

sf_if_iahb_6: Reg<SF_IF_IAHB_6_SPEC>

0x84 - sf_if_iahb_6.

sf_if_iahb_7: Reg<SF_IF_IAHB_7_SPEC>

0x88 - sf_if_iahb_7.

sf_ctrl_prot_en_rd: Reg<SF_CTRL_PROT_EN_RD_SPEC>

0x100 - sf_ctrl_prot_en_rd.

sf_ctrl_prot_en: Reg<SF_CTRL_PROT_EN_SPEC>

0x104 - sf_ctrl_prot_en.

sf_aes_key_r0_0: Reg<SF_AES_KEY_R0_0_SPEC>

0x200 - sf_aes_key_r0_0.

sf_aes_key_r0_1: Reg<SF_AES_KEY_R0_1_SPEC>

0x204 - sf_aes_key_r0_1.

sf_aes_key_r0_2: Reg<SF_AES_KEY_R0_2_SPEC>

0x208 - sf_aes_key_r0_2.

sf_aes_key_r0_3: Reg<SF_AES_KEY_R0_3_SPEC>

0x20c - sf_aes_key_r0_3.

sf_aes_key_r0_4: Reg<SF_AES_KEY_R0_4_SPEC>

0x210 - sf_aes_key_r0_4.

sf_aes_key_r0_5: Reg<SF_AES_KEY_R0_5_SPEC>

0x214 - sf_aes_key_r0_5.

sf_aes_key_r0_6: Reg<SF_AES_KEY_R0_6_SPEC>

0x218 - sf_aes_key_r0_6.

sf_aes_key_r0_7: Reg<SF_AES_KEY_R0_7_SPEC>

0x21c - sf_aes_key_r0_7.

sf_aes_iv_r0_w0: Reg<SF_AES_IV_R0_W0_SPEC>

0x220 - sf_aes_iv_r0_w0.

sf_aes_iv_r0_w1: Reg<SF_AES_IV_R0_W1_SPEC>

0x224 - sf_aes_iv_r0_w1.

sf_aes_iv_r0_w2: Reg<SF_AES_IV_R0_W2_SPEC>

0x228 - sf_aes_iv_r0_w2.

sf_aes_iv_r0_w3: Reg<SF_AES_IV_R0_W3_SPEC>

0x22c - sf_aes_iv_r0_w3.

sf_aes_cfg_r0: Reg<SF_AES_CFG_R0_SPEC>

0x230 - sf_aes_cfg_r0.

sf_aes_key_r1_0: Reg<SF_AES_KEY_R1_0_SPEC>

0x300 - sf_aes_key_r1_0.

sf_aes_key_r1_1: Reg<SF_AES_KEY_R1_1_SPEC>

0x304 - sf_aes_key_r1_1.

sf_aes_key_r1_2: Reg<SF_AES_KEY_R1_2_SPEC>

0x308 - sf_aes_key_r1_2.

sf_aes_key_r1_3: Reg<SF_AES_KEY_R1_3_SPEC>

0x30c - sf_aes_key_r1_3.

sf_aes_key_r1_4: Reg<SF_AES_KEY_R1_4_SPEC>

0x310 - sf_aes_key_r1_4.

sf_aes_key_r1_5: Reg<SF_AES_KEY_R1_5_SPEC>

0x314 - sf_aes_key_r1_5.

sf_aes_key_r1_6: Reg<SF_AES_KEY_R1_6_SPEC>

0x318 - sf_aes_key_r1_6.

sf_aes_key_r1_7: Reg<SF_AES_KEY_R1_7_SPEC>

0x31c - sf_aes_key_r1_7.

sf_aes_iv_r1_w0: Reg<SF_AES_IV_R1_W0_SPEC>

0x320 - sf_aes_iv_r1_w0.

sf_aes_iv_r1_w1: Reg<SF_AES_IV_R1_W1_SPEC>

0x324 - sf_aes_iv_r1_w1.

sf_aes_iv_r1_w2: Reg<SF_AES_IV_R1_W2_SPEC>

0x328 - sf_aes_iv_r1_w2.

sf_aes_iv_r1_w3: Reg<SF_AES_IV_R1_W3_SPEC>

0x32c - sf_aes_iv_r1_w3.

sf_aes_r1: Reg<SF_AES_R1_SPEC>

0x330 - sf_aes_r1.

sf_aes_key_r2_0: Reg<SF_AES_KEY_R2_0_SPEC>

0x400 - sf_aes_key_r2_0.

sf_aes_key_r2_1: Reg<SF_AES_KEY_R2_1_SPEC>

0x404 - sf_aes_key_r2_1.

sf_aes_key_r2_2: Reg<SF_AES_KEY_R2_2_SPEC>

0x408 - sf_aes_key_r2_2.

sf_aes_key_r2_3: Reg<SF_AES_KEY_R2_3_SPEC>

0x40c - sf_aes_key_r2_3.

sf_aes_key_r2_4: Reg<SF_AES_KEY_R2_4_SPEC>

0x410 - sf_aes_key_r2_4.

sf_aes_key_r2_5: Reg<SF_AES_KEY_R2_5_SPEC>

0x414 - sf_aes_key_r2_5.

sf_aes_key_r2_6: Reg<SF_AES_KEY_R2_6_SPEC>

0x418 - sf_aes_key_r2_6.

sf_aes_key_r2_7: Reg<SF_AES_KEY_R2_7_SPEC>

0x41c - sf_aes_key_r2_7.

sf_aes_iv_r2_w0: Reg<SF_AES_IV_R2_W0_SPEC>

0x420 - sf_aes_iv_r2_w0.

sf_aes_iv_r2_w1: Reg<SF_AES_IV_R2_W1_SPEC>

0x424 - sf_aes_iv_r2_w1.

sf_aes_iv_r2_w2: Reg<SF_AES_IV_R2_W2_SPEC>

0x428 - sf_aes_iv_r2_w2.

sf_aes_iv_r2_w3: Reg<SF_AES_IV_R2_W3_SPEC>

0x42c - sf_aes_iv_r2_w3.

sf_aes_r2: Reg<SF_AES_R2_SPEC>

0x430 - sf_aes_r2.

sf_id0_offset: Reg<SF_ID0_OFFSET_SPEC>

0x434 - sf_id0_offset.

sf_id1_offset: Reg<SF_ID1_OFFSET_SPEC>

0x438 - sf_id1_offset.

Auto Trait Implementations

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.