[−][src]Struct bl602_pac::sec_eng::RegisterBlock
Register block
Fields
se_sha_0_ctrl: Reg<SE_SHA_0_CTRL_SPEC>
0x00 - se_sha_0_ctrl.
se_sha_0_msa: Reg<SE_SHA_0_MSA_SPEC>
0x04 - se_sha_0_msa.
se_sha_0_status: Reg<SE_SHA_0_STATUS_SPEC>
0x08 - se_sha_0_status.
se_sha_0_endian: Reg<SE_SHA_0_ENDIAN_SPEC>
0x0c - se_sha_0_endian.
se_sha_0_hash_l_0: Reg<SE_SHA_0_HASH_L_0_SPEC>
0x10 - se_sha_0_hash_l_0.
se_sha_0_hash_l_1: Reg<SE_SHA_0_HASH_L_1_SPEC>
0x14 - se_sha_0_hash_l_1.
se_sha_0_hash_l_2: Reg<SE_SHA_0_HASH_L_2_SPEC>
0x18 - se_sha_0_hash_l_2.
se_sha_0_hash_l_3: Reg<SE_SHA_0_HASH_L_3_SPEC>
0x1c - se_sha_0_hash_l_3.
se_sha_0_hash_l_4: Reg<SE_SHA_0_HASH_L_4_SPEC>
0x20 - se_sha_0_hash_l_4.
se_sha_0_hash_l_5: Reg<SE_SHA_0_HASH_L_5_SPEC>
0x24 - se_sha_0_hash_l_5.
se_sha_0_hash_l_6: Reg<SE_SHA_0_HASH_L_6_SPEC>
0x28 - se_sha_0_hash_l_6.
se_sha_0_hash_l_7: Reg<SE_SHA_0_HASH_L_7_SPEC>
0x2c - se_sha_0_hash_l_7.
se_sha_0_hash_h_0: Reg<SE_SHA_0_HASH_H_0_SPEC>
0x30 - se_sha_0_hash_h_0.
se_sha_0_hash_h_1: Reg<SE_SHA_0_HASH_H_1_SPEC>
0x34 - se_sha_0_hash_h_1.
se_sha_0_hash_h_2: Reg<SE_SHA_0_HASH_H_2_SPEC>
0x38 - se_sha_0_hash_h_2.
se_sha_0_hash_h_3: Reg<SE_SHA_0_HASH_H_3_SPEC>
0x3c - se_sha_0_hash_h_3.
se_sha_0_hash_h_4: Reg<SE_SHA_0_HASH_H_4_SPEC>
0x40 - se_sha_0_hash_h_4.
se_sha_0_hash_h_5: Reg<SE_SHA_0_HASH_H_5_SPEC>
0x44 - se_sha_0_hash_h_5.
se_sha_0_hash_h_6: Reg<SE_SHA_0_HASH_H_6_SPEC>
0x48 - se_sha_0_hash_h_6.
se_sha_0_hash_h_7: Reg<SE_SHA_0_HASH_H_7_SPEC>
0x4c - se_sha_0_hash_h_7.
se_sha_0_link: Reg<SE_SHA_0_LINK_SPEC>
0x50 - se_sha_0_link.
se_sha_0_ctrl_prot: Reg<SE_SHA_0_CTRL_PROT_SPEC>
0xfc - se_sha_0_ctrl_prot.
se_aes_0_ctrl: Reg<SE_AES_0_CTRL_SPEC>
0x100 - se_aes_0_ctrl.
se_aes_0_msa: Reg<SE_AES_0_MSA_SPEC>
0x104 - se_aes_0_msa.
se_aes_0_mda: Reg<SE_AES_0_MDA_SPEC>
0x108 - se_aes_0_mda.
se_aes_0_status: Reg<SE_AES_0_STATUS_SPEC>
0x10c - se_aes_0_status.
se_aes_0_iv_0: Reg<SE_AES_0_IV_0_SPEC>
0x110 - se_aes_0_iv_0.
se_aes_0_iv_1: Reg<SE_AES_0_IV_1_SPEC>
0x114 - se_aes_0_iv_1.
se_aes_0_iv_2: Reg<SE_AES_0_IV_2_SPEC>
0x118 - se_aes_0_iv_2.
se_aes_0_iv_3: Reg<SE_AES_0_IV_3_SPEC>
0x11c - se_aes_0_iv_3.
se_aes_0_key_0: Reg<SE_AES_0_KEY_0_SPEC>
0x120 - se_aes_0_key_0.
se_aes_0_key_1: Reg<SE_AES_0_KEY_1_SPEC>
0x124 - se_aes_0_key_1.
se_aes_0_key_2: Reg<SE_AES_0_KEY_2_SPEC>
0x128 - se_aes_0_key_2.
se_aes_0_key_3: Reg<SE_AES_0_KEY_3_SPEC>
0x12c - se_aes_0_key_3.
se_aes_0_key_4: Reg<SE_AES_0_KEY_4_SPEC>
0x130 - se_aes_0_key_4.
se_aes_0_key_5: Reg<SE_AES_0_KEY_5_SPEC>
0x134 - se_aes_0_key_5.
se_aes_0_key_6: Reg<SE_AES_0_KEY_6_SPEC>
0x138 - se_aes_0_key_6.
se_aes_0_key_7: Reg<SE_AES_0_KEY_7_SPEC>
0x13c - se_aes_0_key_7.
se_aes_0_key_sel_0: Reg<SE_AES_0_KEY_SEL_0_SPEC>
0x140 - se_aes_0_key_sel_0.
se_aes_0_key_sel_1: Reg<SE_AES_0_KEY_SEL_1_SPEC>
0x144 - se_aes_0_key_sel_1.
se_aes_0_endian: Reg<SE_AES_0_ENDIAN_SPEC>
0x148 - se_aes_0_endian.
se_aes_0_sboot: Reg<SE_AES_0_SBOOT_SPEC>
0x14c - se_aes_0_sboot.
se_aes_0_link: Reg<SE_AES_0_LINK_SPEC>
0x150 - se_aes_0_link.
se_aes_0_ctrl_prot: Reg<SE_AES_0_CTRL_PROT_SPEC>
0x1fc - se_aes_0_ctrl_prot.
se_trng_0_ctrl_0: Reg<SE_TRNG_0_CTRL_0_SPEC>
0x200 - se_trng_0_ctrl_0.
se_trng_0_status: Reg<SE_TRNG_0_STATUS_SPEC>
0x204 - se_trng_0_status.
se_trng_0_dout_0: Reg<SE_TRNG_0_DOUT_0_SPEC>
0x208 - se_trng_0_dout_0.
se_trng_0_dout_1: Reg<SE_TRNG_0_DOUT_1_SPEC>
0x20c - se_trng_0_dout_1.
se_trng_0_dout_2: Reg<SE_TRNG_0_DOUT_2_SPEC>
0x210 - se_trng_0_dout_2.
se_trng_0_dout_3: Reg<SE_TRNG_0_DOUT_3_SPEC>
0x214 - se_trng_0_dout_3.
se_trng_0_dout_4: Reg<SE_TRNG_0_DOUT_4_SPEC>
0x218 - se_trng_0_dout_4.
se_trng_0_dout_5: Reg<SE_TRNG_0_DOUT_5_SPEC>
0x21c - se_trng_0_dout_5.
se_trng_0_dout_6: Reg<SE_TRNG_0_DOUT_6_SPEC>
0x220 - se_trng_0_dout_6.
se_trng_0_dout_7: Reg<SE_TRNG_0_DOUT_7_SPEC>
0x224 - se_trng_0_dout_7.
se_trng_0_test: Reg<SE_TRNG_0_TEST_SPEC>
0x228 - se_trng_0_test.
se_trng_0_ctrl_1: Reg<SE_TRNG_0_CTRL_1_SPEC>
0x22c - se_trng_0_ctrl_1.
se_trng_0_ctrl_2: Reg<SE_TRNG_0_CTRL_2_SPEC>
0x230 - se_trng_0_ctrl_2.
se_trng_0_ctrl_3: Reg<SE_TRNG_0_CTRL_3_SPEC>
0x234 - se_trng_0_ctrl_3.
se_trng_0_test_out_0: Reg<SE_TRNG_0_TEST_OUT_0_SPEC>
0x240 - se_trng_0_test_out_0.
se_trng_0_test_out_1: Reg<SE_TRNG_0_TEST_OUT_1_SPEC>
0x244 - se_trng_0_test_out_1.
se_trng_0_test_out_2: Reg<SE_TRNG_0_TEST_OUT_2_SPEC>
0x248 - se_trng_0_test_out_2.
se_trng_0_test_out_3: Reg<SE_TRNG_0_TEST_OUT_3_SPEC>
0x24c - se_trng_0_test_out_3.
se_trng_0_ctrl_prot: Reg<SE_TRNG_0_CTRL_PROT_SPEC>
0x2fc - se_trng_0_ctrl_prot.
se_pka_0_ctrl_0: Reg<SE_PKA_0_CTRL_0_SPEC>
0x300 - se_pka_0_ctrl_0.
se_pka_0_seed: Reg<SE_PKA_0_SEED_SPEC>
0x30c - se_pka_0_seed.
se_pka_0_ctrl_1: Reg<SE_PKA_0_CTRL_1_SPEC>
0x310 - se_pka_0_ctrl_1.
se_pka_0_rw: Reg<SE_PKA_0_RW_SPEC>
0x340 - se_pka_0_rw.
se_pka_0_rw_burst: Reg<SE_PKA_0_RW_BURST_SPEC>
0x360 - se_pka_0_rw_burst.
se_pka_0_ctrl_prot: Reg<SE_PKA_0_CTRL_PROT_SPEC>
0x3fc - se_pka_0_ctrl_prot.
se_cdet_0_ctrl_0: Reg<SE_CDET_0_CTRL_0_SPEC>
0x400 - se_cdet_0_ctrl_0.
se_cdet_0_ctrl_1: Reg<SE_CDET_0_CTRL_1_SPEC>
0x404 - se_cdet_0_ctrl_1.
se_cdet_0_ctrl_prot: Reg<SE_CDET_0_CTRL_PROT_SPEC>
0x4fc - se_cdet_0_ctrl_prot.
se_gmac_0_ctrl_0: Reg<SE_GMAC_0_CTRL_0_SPEC>
0x500 - se_gmac_0_ctrl_0.
se_gmac_0_lca: Reg<SE_GMAC_0_LCA_SPEC>
0x504 - se_gmac_0_lca.
se_gmac_0_status: Reg<SE_GMAC_0_STATUS_SPEC>
0x508 - se_gmac_0_status.
se_gmac_0_ctrl_prot: Reg<SE_GMAC_0_CTRL_PROT_SPEC>
0x5fc - se_gmac_0_ctrl_prot.
se_ctrl_prot_rd: Reg<SE_CTRL_PROT_RD_SPEC>
0xf00 - se_ctrl_prot_rd.
se_ctrl_reserved_0: Reg<SE_CTRL_RESERVED_0_SPEC>
0xf04 - se_ctrl_reserved_0.
se_ctrl_reserved_1: Reg<SE_CTRL_RESERVED_1_SPEC>
0xf08 - se_ctrl_reserved_1.
se_ctrl_reserved_2: Reg<SE_CTRL_RESERVED_2_SPEC>
0xf0c - se_ctrl_reserved_2.
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