[−][src]Struct bl602_pac::rf::RegisterBlock
Register block
Fields
rf_rev: Reg<RF_REV_SPEC>0x00 - Silicon revision
rf_fsm_ctrl_hw: Reg<RF_FSM_CTRL_HW_SPEC>0x04 - Digital Control
rf_fsm_ctrl_sw: Reg<RF_FSM_CTRL_SW_SPEC>0x08 - rfsm status reg
rfctrl_hw_en: Reg<RFCTRL_HW_EN_SPEC>0x0c - Control logic switch
temp_comp: Reg<TEMP_COMP_SPEC>0x10 - temp_comp.
rfcal_status: Reg<RFCAL_STATUS_SPEC>0x14 - rfcal_status.
rfcal_status2: Reg<RFCAL_STATUS2_SPEC>0x18 - rfcal_status2.
rfcal_ctrlen: Reg<RFCAL_CTRLEN_SPEC>0x1c - Calibration mode register
rfcal_stateen: Reg<RFCAL_STATEEN_SPEC>0x20 - rf calibration state enabl in full cal list
saradc_resv: Reg<SARADC_RESV_SPEC>0x24 - SARADC Control Registers
rf_base_ctrl1: Reg<RF_BASE_CTRL1_SPEC>0x28 - ZRF Control register 0
rf_base_ctrl2: Reg<RF_BASE_CTRL2_SPEC>0x2c - ZRF Control register 0
pucr1: Reg<PUCR1_SPEC>0x30 - pucr1.
pucr1_hw: Reg<PUCR1_HW_SPEC>0x34 - read only from hardware logic
pucr2: Reg<PUCR2_SPEC>0x38 - pucr2.
pucr2_hw: Reg<PUCR2_HW_SPEC>0x3c - pucr2_hw.
ppu_ctrl_hw: Reg<PPU_CTRL_HW_SPEC>0x40 - ppu_ctrl_hw.
pud_ctrl_hw: Reg<PUD_CTRL_HW_SPEC>0x44 - pud_ctrl_hw.
trx_gain1: Reg<TRX_GAIN1_SPEC>0x48 - gain control1
trx_gain_hw: Reg<TRX_GAIN_HW_SPEC>0x4c - trx gain hardware readback
ten_dc: Reg<TEN_DC_SPEC>0x50 - dc test register
ten_dig: Reg<TEN_DIG_SPEC>0x54 - digital test register
ten_ac: Reg<TEN_AC_SPEC>0x58 - ac test register
pmip_mv2aon: Reg<PMIP_MV2AON_SPEC>0x5c - pmip_mv2aon.
cip: Reg<CIP_SPEC>0x60 - RX normal bias mode registers
pa1: Reg<PA1_SPEC>0x64 - pa1.
pa2: Reg<PA2_SPEC>0x68 - RX normal bias mode registers
tmx: Reg<TMX_SPEC>0x6c - tmx.
tbb: Reg<TBB_SPEC>0x70 - tbb.
lna: Reg<LNA_SPEC>0x74 - lna.
rmxgm: Reg<RMXGM_SPEC>0x78 - rmxgm.
rbb1: Reg<RBB1_SPEC>0x7c - rbb1.
rbb2: Reg<RBB2_SPEC>0x80 - rbb2.
rbb3: Reg<RBB3_SPEC>0x84 - rbb3.
rbb4: Reg<RBB4_SPEC>0x88 - rbb4.
adda1: Reg<ADDA1_SPEC>0x8c - adda1.
adda2: Reg<ADDA2_SPEC>0x90 - adda2.
vco1: Reg<VCO1_SPEC>0xa0 - vco1.
vco2: Reg<VCO2_SPEC>0xa4 - vco2.
vco3: Reg<VCO3_SPEC>0xa8 - vco3.
vco4: Reg<VCO4_SPEC>0xac - vco4.
pfdcp: Reg<PFDCP_SPEC>0xb0 - pfdcp.
lo: Reg<LO_SPEC>0xb4 - lo.
fbdv: Reg<FBDV_SPEC>0xb8 - fbdv.
lodist: Reg<LODIST_SPEC>0xbc - lodist.
sdm1: Reg<SDM1_SPEC>0xc0 - sdm1.
sdm2: Reg<SDM2_SPEC>0xc4 - sdm2.
sdm3: Reg<SDM3_SPEC>0xc8 - sdm3.
rf_resv_reg_0: Reg<RF_RESV_REG_0_SPEC>0xec - rf_resv_reg_0.
rf_resv_reg_1: Reg<RF_RESV_REG_1_SPEC>0xf0 - rf_resv_reg_1.
rf_resv_reg_2: Reg<RF_RESV_REG_2_SPEC>0xf4 - rf_resv_reg_2.
rrf_gain_index1: Reg<RRF_GAIN_INDEX1_SPEC>0xf8 - rrf_gain_index1.
rrf_gain_index2: Reg<RRF_GAIN_INDEX2_SPEC>0xfc - rrf_gain_index2.
lna_ctrl_hw_mux: Reg<LNA_CTRL_HW_MUX_SPEC>0x100 - lna_ctrl_hw_mux.
rbb_gain_index1: Reg<RBB_GAIN_INDEX1_SPEC>0x104 - rbb_gain_index1.
rbb_gain_index2: Reg<RBB_GAIN_INDEX2_SPEC>0x108 - rbb_gain_index2.
rbb_gain_index3: Reg<RBB_GAIN_INDEX3_SPEC>0x10c - rbb_gain_index3.
rbb_gain_index4: Reg<RBB_GAIN_INDEX4_SPEC>0x110 - rbb_gain_index4.
rbb_gain_index5: Reg<RBB_GAIN_INDEX5_SPEC>0x114 - rbb_gain_index5.
tbb_gain_index1: Reg<TBB_GAIN_INDEX1_SPEC>0x118 - tbb_gain_index1.
tbb_gain_index2: Reg<TBB_GAIN_INDEX2_SPEC>0x11c - tbb_gain_index2.
tbb_gain_index3: Reg<TBB_GAIN_INDEX3_SPEC>0x120 - tbb_gain_index3.
tbb_gain_index4: Reg<TBB_GAIN_INDEX4_SPEC>0x124 - tbb_gain_index4.
pa_reg_ctrl_hw1: Reg<PA_REG_CTRL_HW1_SPEC>0x128 - pa_reg_ctrl_hw1.
pa_reg_ctrl_hw2: Reg<PA_REG_CTRL_HW2_SPEC>0x12c - pa_reg_ctrl_hw2.
pa_reg_wifi_ctrl_hw: Reg<PA_REG_WIFI_CTRL_HW_SPEC>0x130 - pa_reg_wifi_ctrl_hw.
adda_reg_ctrl_hw: Reg<ADDA_REG_CTRL_HW_SPEC>0x134 - adda_reg_ctrl_hw.
lo_reg_ctrl_hw1: Reg<LO_REG_CTRL_HW1_SPEC>0x138 - lo_reg_ctrl_hw1.
lo_cal_ctrl_hw1: Reg<LO_CAL_CTRL_HW1_SPEC>0x13c - lo_cal_ctrl_hw1.
lo_cal_ctrl_hw2: Reg<LO_CAL_CTRL_HW2_SPEC>0x140 - lo_cal_ctrl_hw2.
lo_cal_ctrl_hw3: Reg<LO_CAL_CTRL_HW3_SPEC>0x144 - lo_cal_ctrl_hw3.
lo_cal_ctrl_hw4: Reg<LO_CAL_CTRL_HW4_SPEC>0x148 - lo_cal_ctrl_hw4.
lo_cal_ctrl_hw5: Reg<LO_CAL_CTRL_HW5_SPEC>0x14c - lo_cal_ctrl_hw5.
lo_cal_ctrl_hw6: Reg<LO_CAL_CTRL_HW6_SPEC>0x150 - lo_cal_ctrl_hw6.
lo_cal_ctrl_hw7: Reg<LO_CAL_CTRL_HW7_SPEC>0x154 - lo_cal_ctrl_hw7.
lo_cal_ctrl_hw8: Reg<LO_CAL_CTRL_HW8_SPEC>0x158 - lo_cal_ctrl_hw8.
lo_cal_ctrl_hw9: Reg<LO_CAL_CTRL_HW9_SPEC>0x15c - lo_cal_ctrl_hw9.
lo_cal_ctrl_hw10: Reg<LO_CAL_CTRL_HW10_SPEC>0x160 - lo_cal_ctrl_hw10.
lo_cal_ctrl_hw11: Reg<LO_CAL_CTRL_HW11_SPEC>0x164 - lo_cal_ctrl_hw11.
rosdac_ctrl_hw1: Reg<ROSDAC_CTRL_HW1_SPEC>0x168 - rosdac_ctrl_hw1.
rosdac_ctrl_hw2: Reg<ROSDAC_CTRL_HW2_SPEC>0x16c - rosdac_ctrl_hw2.
rxiq_ctrl_hw1: Reg<RXIQ_CTRL_HW1_SPEC>0x170 - rxiq_ctrl_hw1.
rxiq_ctrl_hw2: Reg<RXIQ_CTRL_HW2_SPEC>0x174 - rxiq_ctrl_hw2.
rxiq_ctrl_hw3: Reg<RXIQ_CTRL_HW3_SPEC>0x178 - rxiq_ctrl_hw3.
rxiq_ctrl_hw4: Reg<RXIQ_CTRL_HW4_SPEC>0x17c - rxiq_ctrl_hw4.
tosdac_ctrl_hw1: Reg<TOSDAC_CTRL_HW1_SPEC>0x180 - tosdac_ctrl_hw1.
tosdac_ctrl_hw2: Reg<TOSDAC_CTRL_HW2_SPEC>0x184 - tosdac_ctrl_hw2.
tosdac_ctrl_hw3: Reg<TOSDAC_CTRL_HW3_SPEC>0x188 - tosdac_ctrl_hw3.
tosdac_ctrl_hw4: Reg<TOSDAC_CTRL_HW4_SPEC>0x18c - tosdac_ctrl_hw4.
tx_iq_gain_hw0: Reg<TX_IQ_GAIN_HW0_SPEC>0x190 - tx_iq_gain_hw0.
tx_iq_gain_hw1: Reg<TX_IQ_GAIN_HW1_SPEC>0x194 - tx_iq_gain_hw1.
tx_iq_gain_hw2: Reg<TX_IQ_GAIN_HW2_SPEC>0x198 - tx_iq_gain_hw2.
tx_iq_gain_hw3: Reg<TX_IQ_GAIN_HW3_SPEC>0x19c - tx_iq_gain_hw3.
tx_iq_gain_hw4: Reg<TX_IQ_GAIN_HW4_SPEC>0x1a0 - tx_iq_gain_hw4.
tx_iq_gain_hw5: Reg<TX_IQ_GAIN_HW5_SPEC>0x1a4 - tx_iq_gain_hw5.
tx_iq_gain_hw6: Reg<TX_IQ_GAIN_HW6_SPEC>0x1a8 - tx_iq_gain_hw6.
tx_iq_gain_hw7: Reg<TX_IQ_GAIN_HW7_SPEC>0x1ac - tx_iq_gain_hw7.
lo_sdm_ctrl_hw1: Reg<LO_SDM_CTRL_HW1_SPEC>0x1b0 - lo_sdm_ctrl_hw1.
lo_sdm_ctrl_hw2: Reg<LO_SDM_CTRL_HW2_SPEC>0x1b4 - lo_sdm_ctrl_hw2.
lo_sdm_ctrl_hw3: Reg<LO_SDM_CTRL_HW3_SPEC>0x1b8 - lo_sdm_ctrl_hw3.
lo_sdm_ctrl_hw4: Reg<LO_SDM_CTRL_HW4_SPEC>0x1bc - lo_sdm_ctrl_hw4.
lo_sdm_ctrl_hw5: Reg<LO_SDM_CTRL_HW5_SPEC>0x1c0 - lo_sdm_ctrl_hw5.
lo_sdm_ctrl_hw6: Reg<LO_SDM_CTRL_HW6_SPEC>0x1c4 - lo_sdm_ctrl_hw6.
lo_sdm_ctrl_hw7: Reg<LO_SDM_CTRL_HW7_SPEC>0x1c8 - lo_sdm_ctrl_hw7.
lo_sdm_ctrl_hw8: Reg<LO_SDM_CTRL_HW8_SPEC>0x1cc - lo_sdm_ctrl_hw8.
rbb_bw_ctrl_hw: Reg<RBB_BW_CTRL_HW_SPEC>0x1d0 - rbb_bw_ctrl_hw.
singen_ctrl0: Reg<SINGEN_CTRL0_SPEC>0x20c - singen_ctrl0.
singen_ctrl1: Reg<SINGEN_CTRL1_SPEC>0x210 - singen_ctrl1.
singen_ctrl2: Reg<SINGEN_CTRL2_SPEC>0x214 - singen_ctrl2.
singen_ctrl3: Reg<SINGEN_CTRL3_SPEC>0x218 - singen_ctrl3.
singen_ctrl4: Reg<SINGEN_CTRL4_SPEC>0x21c - singen_ctrl4.
rfif_dfe_ctrl0: Reg<RFIF_DFE_CTRL0_SPEC>0x220 - rfif_dfe_ctrl0.
rfif_test_read: Reg<RFIF_TEST_READ_SPEC>0x224 - rfif_test_read.
rfif_dig_ctrl: Reg<RFIF_DIG_CTRL_SPEC>0x228 - rfif_dig_ctrl.
rf_data_temp_0: Reg<RF_DATA_TEMP_0_SPEC>0x22c - rf_data_temp_0.
rf_data_temp_1: Reg<RF_DATA_TEMP_1_SPEC>0x230 - rf_data_temp_1.
rf_data_temp_2: Reg<RF_DATA_TEMP_2_SPEC>0x234 - rf_data_temp_2.
rf_data_temp_3: Reg<RF_DATA_TEMP_3_SPEC>0x238 - rf_data_temp_3.
rf_sram_ctrl0: Reg<RF_SRAM_CTRL0_SPEC>0x23c - rf_sram_ctrl0.
rf_sram_ctrl1: Reg<RF_SRAM_CTRL1_SPEC>0x240 - rf_sram_ctrl1.
rf_sram_ctrl2: Reg<RF_SRAM_CTRL2_SPEC>0x244 - rf_sram_ctrl2.
rf_sram_ctrl3: Reg<RF_SRAM_CTRL3_SPEC>0x248 - rf_sram_ctrl3.
rf_sram_ctrl4: Reg<RF_SRAM_CTRL4_SPEC>0x24c - rf_sram_ctrl4.
rf_sram_ctrl5: Reg<RF_SRAM_CTRL5_SPEC>0x250 - rf_sram_ctrl5.
rf_sram_ctrl6: Reg<RF_SRAM_CTRL6_SPEC>0x254 - rf_sram_ctrl6.
rf_ical_ctrl0: Reg<RF_ICAL_CTRL0_SPEC>0x258 - rf_ical_ctrl0.
rf_ical_ctrl1: Reg<RF_ICAL_CTRL1_SPEC>0x25c - rf_ical_ctrl1.
rf_ical_ctrl2: Reg<RF_ICAL_CTRL2_SPEC>0x260 - rf_ical_ctrl2.
rf_fsm_ctrl0: Reg<RF_FSM_CTRL0_SPEC>0x264 - rf_fsm_ctrl0.
rf_fsm_ctrl1: Reg<RF_FSM_CTRL1_SPEC>0x268 - rf_fsm_ctrl1.
rf_fsm_ctrl2: Reg<RF_FSM_CTRL2_SPEC>0x26c - rf_fsm_ctrl2.
rf_pkdet_ctrl0: Reg<RF_PKDET_CTRL0_SPEC>0x270 - rf_pkdet_ctrl0.
dfe_ctrl_0: Reg<DFE_CTRL_0_SPEC>0x600 - dfe_ctrl_0.
dfe_ctrl_1: Reg<DFE_CTRL_1_SPEC>0x604 - dfe_ctrl_1.
dfe_ctrl_2: Reg<DFE_CTRL_2_SPEC>0x608 - dfe_ctrl_2.
dfe_ctrl_3: Reg<DFE_CTRL_3_SPEC>0x60c - dfe_ctrl_3.
dfe_ctrl_4: Reg<DFE_CTRL_4_SPEC>0x610 - dfe_ctrl_4.
dfe_ctrl_5: Reg<DFE_CTRL_5_SPEC>0x614 - dfe_ctrl_5.
dfe_ctrl_6: Reg<DFE_CTRL_6_SPEC>0x618 - dfe_ctrl_6.
dfe_ctrl_7: Reg<DFE_CTRL_7_SPEC>0x61c - dfe_ctrl_7.
dfe_ctrl_8: Reg<DFE_CTRL_8_SPEC>0x620 - dfe_ctrl_8.
dfe_ctrl_9: Reg<DFE_CTRL_9_SPEC>0x624 - dfe_ctrl_9.
dfe_ctrl_10: Reg<DFE_CTRL_10_SPEC>0x628 - dfe_ctrl_10.
dfe_ctrl_11: Reg<DFE_CTRL_11_SPEC>0x62c - dfe_ctrl_11.
dfe_ctrl_12: Reg<DFE_CTRL_12_SPEC>0x630 - dfe_ctrl_12.
dfe_ctrl_13: Reg<DFE_CTRL_13_SPEC>0x634 - dfe_ctrl_13.
dfe_ctrl_14: Reg<DFE_CTRL_14_SPEC>0x638 - dfe_ctrl_14.
dfe_ctrl_15: Reg<DFE_CTRL_15_SPEC>0x63c - dfe_ctrl_15.
dfe_ctrl_16: Reg<DFE_CTRL_16_SPEC>0x640 - dfe_ctrl_16.
dfe_ctrl_17: Reg<DFE_CTRL_17_SPEC>0x644 - dfe_ctrl_17.
dfe_ctrl_18: Reg<DFE_CTRL_18_SPEC>0x648 - dfe_ctrl_18.
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